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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id m9sm1342538pjs.18.2020.07.05.13.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jul 2020 13:31:53 -0700 (PDT) Date: Sun, 5 Jul 2020 13:31:52 -0700 From: Kees Cook To: Guo Ren Subject: Re: [PATCH] riscv: Add STACKPROTECTOR supported Message-ID: <202007051328.FE9EF99@keescook> References: <1593930255-12378-1-git-send-email-guoren@kernel.org> <202007042350.4C153C4F8@keescook> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200705_163156_952479_BCCC7D3F X-CRM114-Status: GOOD ( 17.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Guo Ren , Anup Patel , Palmer Dabbelt , Linux Kernel Mailing List , linux-csky@vger.kernel.org, Atish Patra , Albert Ou , Masami Hiramatsu , Zong Li , Paul Walmsley , Greentime Hu , linux-riscv , Greentime Hu , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, Jul 05, 2020 at 10:16:14PM +0800, Guo Ren wrote: > On Sun, Jul 5, 2020 at 2:53 PM Kees Cook wrote: > > On Sun, Jul 05, 2020 at 06:24:15AM +0000, guoren@kernel.org wrote: > > > +static __always_inline void boot_init_stack_canary(void) > > > +{ > > > + unsigned long canary; > > > + > > > + /* Try to get a semi random initial value. */ > > > + get_random_bytes(&canary, sizeof(canary)); > > > + canary ^= LINUX_VERSION_CODE; > > > + canary &= CANARY_MASK; > > > > Does riscv have any kind of instruction counters or other trivial timers > > that could be mixed in here? (e.g. x86's TSC) > Do you mean: > get_random_bytes(&canary, sizeof(canary)); > + canary += get_cycles64() + (get_cycles64() << 32UL); > canary ^= LINUX_VERSION_CODE; > canary &= CANARY_MASK; > > Ok ? Sure -- I assume get_cycles64() is architecturally "simple"? (i.e. it doesn't require that the entire time-keeping subsystem has started?) > > > > > + > > > + current->stack_canary = canary; > > > + __stack_chk_guard = current->stack_canary; > > > > What's needed for riscv to support a per-task canary? (e.g. x86's TLS or > > arm64's register-specific methods) > Some archs change __stack_chk_guard in _switch_to of entry.S, but it > depends on !CONFIG_SMP. Oh, funny. I hadn't actually noticed that logic for the !CONFIG_SMP cases. I see to problem with that, but the more important case, I think is the per-task canaries. > #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) > get value from next_task->stack_canary > store value to __stack_chk_guard > #endif > > It's a so limitation solution for per-task canary, so I didn't copy it > into riscv? Right -- it's a limited solution. On the other had, is !CONFIG_SMP expected to be a common config for riscv? If so, it's worth adding. If not, I'd say skip it. (Though it looks very simple to do...) -- Kees Cook _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv