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From: kernel test robot <lkp@intel.com>
To: Zong Li <zong.li@sifive.com>,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	david.abdurachmanov@sifive.com, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: Palmer Dabbelt <palmerdabbelt@google.com>,
	kbuild-all@lists.01.org, Zong Li <zong.li@sifive.com>
Subject: Re: [PATCH v2 3/3] riscv: Add cache information in AUX vector
Date: Fri, 28 Aug 2020 12:45:21 +0800	[thread overview]
Message-ID: <202008281227.ovrwo5u7%lkp@intel.com> (raw)
In-Reply-To: <f9199795d6e9bae73f49583c494505e0a4983c61.1598515355.git.zong.li@sifive.com>

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Hi Zong,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.9-rc2 next-20200827]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Zong-Li/Get-cache-information-from-userland/20200827-162439
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 15bc20c6af4ceee97a1f90b43c0e386643c071b4
config: riscv-randconfig-s032-20200827 (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.2-191-g10164920-dirty
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=riscv 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)

>> arch/riscv/kernel/cacheinfo.c:39:16: sparse: sparse: Using plain integer as NULL pointer

# https://github.com/0day-ci/linux/commit/a51c248ba0626069792c3f84c8879f685f4a1ff6
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Zong-Li/Get-cache-information-from-userland/20200827-162439
git checkout a51c248ba0626069792c3f84c8879f685f4a1ff6
vim +39 arch/riscv/kernel/cacheinfo.c

    26	
    27	static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
    28	{
    29		struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(smp_processor_id());
    30		struct cacheinfo *this_leaf;
    31		int index;
    32	
    33		for (index = 0; index < this_cpu_ci->num_leaves; index++) {
    34			this_leaf = this_cpu_ci->info_list + index;
    35			if (this_leaf->level == level && this_leaf->type == type)
    36				return this_leaf;
    37		}
    38	
  > 39		return 0;
    40	}
    41	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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_______________________________________________
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  reply	other threads:[~2020-09-17 15:24 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-27  8:22 [PATCH v2 0/3] Get cache information from userland Zong Li
2020-08-27  8:22 ` [PATCH v2 1/3] riscv: Set more data to cacheinfo Zong Li
2020-08-27  8:22 ` [PATCH v2 2/3] riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO Zong Li
2020-08-27  8:22 ` [PATCH v2 3/3] riscv: Add cache information in AUX vector Zong Li
2020-08-28  4:45   ` kernel test robot [this message]
2020-08-31 11:59   ` Dan Carpenter
2020-09-04 19:17 ` [PATCH v2 0/3] Get cache information from userland Palmer Dabbelt

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