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Tue, 15 Sep 2020 08:22:05 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id b8sm7756889ioa.33.2020.09.15.08.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2020 08:22:04 -0700 (PDT) Received: (nullmailer pid 1970179 invoked by uid 1000); Tue, 15 Sep 2020 15:22:01 -0000 Date: Tue, 15 Sep 2020 09:22:01 -0600 From: Rob Herring To: Yash Shah Subject: Re: [PATCH v2 0/3] SiFive DDR controller and EDAC support Message-ID: <20200915152201.GA1940827@bogus> References: <1599457679-8947-1-git-send-email-yash.shah@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1599457679-8947-1-git-send-email-yash.shah@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200915_112206_528779_4CB6D8A2 X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, tony.luck@intel.com, james.morse@arm.com, linux-kernel@vger.kernel.org, rrichter@marvell.com, sachin.ghadi@sifive.com, aou@eecs.berkeley.edu, bp@alien8.de, paul.walmsley@sifive.com, palmer@dabbelt.com, linux-riscv@lists.infradead.org, mchehab@kernel.org, linux-edac@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Sep 07, 2020 at 11:17:56AM +0530, Yash Shah wrote: > The series add supports for SiFive DDR controller driver. This driver > is use to manage the Cadence DDR controller present in SiFive SoCs. > Currently it manages only the EDAC feature of the DDR controller. > The series also adds Memory controller EDAC support for SiFive platform. > It register for notifier event from SiFive DDR controller driver. This is an odd split and notifiers aren't a great interface. Why not just combine these? Is there some other DDR controller functionality planned for the driver? FYI, highbank_mc_edac.c is also a Cadence controller. IIRC, the register layout changes for every customer/design. Rob _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv