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Tue, 15 Sep 2020 08:24:38 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id i9sm4609484ils.34.2020.09.15.08.24.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2020 08:24:37 -0700 (PDT) Received: (nullmailer pid 1973925 invoked by uid 1000); Tue, 15 Sep 2020 15:24:35 -0000 Date: Tue, 15 Sep 2020 09:24:35 -0600 From: Rob Herring To: Yash Shah Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs Message-ID: <20200915152435.GB1940827@bogus> References: <1599457679-8947-1-git-send-email-yash.shah@sifive.com> <1599457679-8947-2-git-send-email-yash.shah@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1599457679-8947-2-git-send-email-yash.shah@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200915_112439_493922_B349F6AD X-CRM114-Status: GOOD ( 18.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, tony.luck@intel.com, james.morse@arm.com, linux-kernel@vger.kernel.org, rrichter@marvell.com, sachin.ghadi@sifive.com, aou@eecs.berkeley.edu, bp@alien8.de, paul.walmsley@sifive.com, palmer@dabbelt.com, linux-riscv@lists.infradead.org, mchehab@kernel.org, linux-edac@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Sep 07, 2020 at 11:17:57AM +0530, Yash Shah wrote: > Add device tree bindings for SiFive FU540 DDR controller driver > > Signed-off-by: Yash Shah > Reviewed-by: Palmer Dabbelt > Acked-by: Palmer Dabbelt > --- > .../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++++++++++++++++++++++ Bindings are organized by function, not vendor/arch generally. This goes in bindings/memory-controllers/. > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml > new file mode 100644 > index 0000000..0288119 > --- /dev/null > +++ b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml > @@ -0,0 +1,41 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/riscv/sifive-ddr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive DDR memory controller binding > + > +description: | > + The Sifive DDR controller driver is used to manage the Cadence DDR > + controller present in SiFive FU540-C000 SoC. Currently the driver is > + used to manage EDAC feature of the DDR controller. Bindings describe h/w not drivers. What a driver supports is irrelevant. > + > +maintainers: > + - Yash Shah > + > +properties: > + compatible: > + enum: > + - sifive,fu540-c000-ddr > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + memory-controller@100b0000 { > + compatible = "sifive,fu540-c000-ddr"; > + reg = <0x100b0000 0x4000>; > + interrupts = <31>; > + }; > -- > 2.7.4 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv