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Sat, 21 Nov 2020 04:54:48 -0800 (PST) Received: from xps15 ([2607:fb90:5feb:6270:cdf7:680e:59f2:6ccd]) by smtp.gmail.com with ESMTPSA id s134sm4045140qke.99.2020.11.21.04.54.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Nov 2020 04:54:48 -0800 (PST) Received: (nullmailer pid 2081252 invoked by uid 1000); Sat, 21 Nov 2020 12:54:43 -0000 Date: Sat, 21 Nov 2020 06:54:43 -0600 From: Rob Herring To: Yash Shah Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740 Message-ID: <20201121125443.GA2076465@robh.at.kernel.org> References: <1605172274-44916-1-git-send-email-yash.shah@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1605172274-44916-1-git-send-email-yash.shah@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201121_183913_900538_94D30C11 X-CRM114-Status: GOOD ( 18.46 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, aou@eecs.berkeley.edu, anup@brainfault.org, paul.walmsley@sifive.com, linux-kernel@vger.kernel.org, wsa@kernel.org, sachin.ghadi@sifive.com, palmer@dabbelt.com, sagar.kadam@sifive.com, Jonathan.Cameron@huawei.com, linux-riscv@lists.infradead.org, bp@suse.de, sam@ravnborg.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote: > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > compared to 3 in FU540. Update the DT documentation accordingly with > "compatible" and "interrupt" property changes. > > Signed-off-by: Yash Shah > --- > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 +++++++++++++++++----- > 1 file changed, 26 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > index efc0198..4873d5c 100644 > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > @@ -27,6 +27,7 @@ select: > items: > - enum: > - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > > required: > - compatible > @@ -34,7 +35,9 @@ select: > properties: > compatible: > items: > - - const: sifive,fu540-c000-ccache > + - enum: > + - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > - const: cache > > cache-block-size: > @@ -51,12 +54,6 @@ properties: > > cache-unified: true > > - interrupts: > - description: | > - Must contain entries for DirError, DataError and DataFail signals. > - minItems: 3 > - maxItems: 3 Keep this here and just change maxItems to 4. Really, what each interrupt is should be listed out as an 'items' entry. > - > reg: > maxItems: 1 > > @@ -67,6 +64,28 @@ properties: > The reference to the reserved-memory for the L2 Loosely Integrated Memory region. > The reserved memory node should be defined as per the bindings in reserved-memory.txt. > > +if: > + properties: > + compatible: > + contains: > + const: sifive,fu540-c000-ccache > + > +then: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError and DataFail signals. > + minItems: 3 > + maxItems: 3 Here you just need 'maxItems: 3'. > + > +else: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DirFail, DataError, DataFail signals. DirFail should be last so you keep the same indices. > + minItems: 4 > + maxItems: 4 And 'minItems: 4' > + > additionalProperties: false > > required: > -- > 2.7.4 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv