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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id m22sm1408338ooj.43.2021.02.04.15.48.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Feb 2021 15:48:21 -0800 (PST) Received: (nullmailer pid 1351403 invoked by uid 1000); Thu, 04 Feb 2021 23:48:19 -0000 Date: Thu, 4 Feb 2021 17:48:19 -0600 From: Rob Herring To: Damien Le Moal Subject: Re: [PATCH v15 04/16] dt-bindings: update sifive plic compatible string Message-ID: <20210204234819.GA1348461@robh.at.kernel.org> References: <20210203125913.390949-1-damien.lemoal@wdc.com> <20210203125913.390949-5-damien.lemoal@wdc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210203125913.390949-5-damien.lemoal@wdc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210204_184823_838228_9F82FC78 X-CRM114-Status: GOOD ( 18.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Anup Patel , Sean Anderson , Atish Patra , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Feb 03, 2021 at 09:59:01PM +0900, Damien Le Moal wrote: > Add the compatible string "canaan,k210-plic" to the Sifive plic bindings > to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan > Kendryte K210 SoC. The description is also updated to reflect this > change, that is, that SoCs from other vendors may also use this plic > implementation. > > Cc: Paul Walmsley > Cc: Rob Herring > Cc: devicetree@vger.kernel.org > Signed-off-by: Damien Le Moal > Reviewed-by: Atish Patra > --- > .../sifive,plic-1.0.0.yaml | 20 ++++++++++++------- > 1 file changed, 13 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index b9a61c9f7530..04ed7a03c97e 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: SiFive Platform-Level Interrupt Controller (PLIC) > > description: > - SiFive SOCs include an implementation of the Platform-Level Interrupt Controller > - (PLIC) high-level specification in the RISC-V Privileged Architecture > - specification. The PLIC connects all external interrupts in the system to all > - hart contexts in the system, via the external interrupt source in each hart. > + SiFive SoCs and other RISC-V SoCs include an implementation of the > + Platform-Level Interrupt Controller (PLIC) high-level specification in > + the RISC-V Privileged Architecture specification. The PLIC connects all > + external interrupts in the system to all hart contexts in the system, via > + the external interrupt source in each hart. > > A hart context is a privilege mode in a hardware execution thread. For example, > in an 4 core system with 2-way SMT, you have 8 harts and probably at least two > @@ -41,9 +42,14 @@ maintainers: > > properties: > compatible: > - items: > - - const: sifive,fu540-c000-plic Change this to an 'enum' and add 'canaan,k210-plic'. > - - const: sifive,plic-1.0.0 > + oneOf: > + - items: > + - const: sifive,fu540-c000-plic > + - const: sifive,plic-1.0.0 > + > + - items: > + - const: canaan,k210-plic > + - const: sifive,plic-1.0.0 > > reg: > maxItems: 1 > -- > 2.29.2 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv