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Wed, 19 May 2021 09:25:05 GMT Received: from pps.reinject (localhost [127.0.0.1]) by aserp3020.oracle.com with ESMTP id 38mechm6e3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 19 May 2021 09:25:05 +0000 Received: from aserp3020.oracle.com (aserp3020.oracle.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 14J9Lvis123188; Wed, 19 May 2021 09:25:04 GMT Received: from userv0122.oracle.com (userv0122.oracle.com [156.151.31.75]) by aserp3020.oracle.com with ESMTP id 38mechm6c6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 19 May 2021 09:25:04 +0000 Received: from abhmp0016.oracle.com (abhmp0016.oracle.com [141.146.116.22]) by userv0122.oracle.com (8.14.4/8.14.4) with ESMTP id 14J9Owe8013238; Wed, 19 May 2021 09:24:58 GMT Received: from kadam (/41.212.42.34) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 19 May 2021 02:24:57 -0700 Date: Wed, 19 May 2021 12:24:41 +0300 From: Dan Carpenter To: Anup Patel Cc: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Paolo Bonzini , Jonathan Corbet , Greg Kroah-Hartman , Alexander Graf , Atish Patra , Alistair Francis , Damien Le Moal , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH v18 02/18] RISC-V: Add initial skeletal KVM support Message-ID: <20210519092441.GQ1955@kadam> References: <20210519033553.1110536-1-anup.patel@wdc.com> <20210519033553.1110536-3-anup.patel@wdc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210519033553.1110536-3-anup.patel@wdc.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-Proofpoint-ORIG-GUID: WFKODEbKdUYqjC4MuMXLdYlfJUXJ4yB5 X-Proofpoint-GUID: WFKODEbKdUYqjC4MuMXLdYlfJUXJ4yB5 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=9988 signatures=668683 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 suspectscore=0 clxscore=1011 adultscore=0 bulkscore=0 phishscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2105190068 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210519_022518_730320_147D7404 X-CRM114-Status: GOOD ( 28.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, May 19, 2021 at 09:05:37AM +0530, Anup Patel wrote: > +int kvm_arch_hardware_enable(void) > +{ > + unsigned long hideleg, hedeleg; > + > + hedeleg = 0; > + hedeleg |= (1UL << EXC_INST_MISALIGNED); You may as well use BIT_UL(EXC_INST_MISALIGNED) for all of these. There is a Coccinelle script to convert these so please just make it standard like everyone else. > + hedeleg |= (1UL << EXC_BREAKPOINT); > + hedeleg |= (1UL << EXC_SYSCALL); > + hedeleg |= (1UL << EXC_INST_PAGE_FAULT); > + hedeleg |= (1UL << EXC_LOAD_PAGE_FAULT); > + hedeleg |= (1UL << EXC_STORE_PAGE_FAULT); > + csr_write(CSR_HEDELEG, hedeleg); > + > + hideleg = 0; > + hideleg |= (1UL << IRQ_VS_SOFT); > + hideleg |= (1UL << IRQ_VS_TIMER); > + hideleg |= (1UL << IRQ_VS_EXT); > + csr_write(CSR_HIDELEG, hideleg); > + > + csr_write(CSR_HCOUNTEREN, -1UL); > + > + csr_write(CSR_HVIP, 0); > + > + return 0; > +} > + > +void kvm_arch_hardware_disable(void) > +{ > + csr_write(CSR_HEDELEG, 0); > + csr_write(CSR_HIDELEG, 0); > +} > + > +int kvm_arch_init(void *opaque) > +{ > + if (!riscv_isa_extension_available(NULL, h)) { > + kvm_info("hypervisor extension not available\n"); > + return -ENODEV; > + } > + > + if (sbi_spec_is_0_1()) { > + kvm_info("require SBI v0.2 or higher\n"); > + return -ENODEV; > + } > + > + if (sbi_probe_extension(SBI_EXT_RFENCE) <= 0) { sbi_probe_extension() never returns zero. > + kvm_info("require SBI RFENCE extension\n"); > + return -ENODEV; > + } > + > + kvm_info("hypervisor extension available\n"); > + > + return 0; > +} > + > +void kvm_arch_exit(void) > +{ > +} > + > +static int riscv_kvm_init(void) > +{ > + return kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); > +} > +module_init(riscv_kvm_init); [ snip ] > +int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) > +{ > + int ret; > + struct kvm_cpu_trap trap; > + struct kvm_run *run = vcpu->run; > + > + vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); > + > + /* Process MMIO value returned from user-space */ > + if (run->exit_reason == KVM_EXIT_MMIO) { > + ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run); > + if (ret) { > + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); > + return ret; > + } > + } > + > + if (run->immediate_exit) { > + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); > + return -EINTR; > + } > + > + vcpu_load(vcpu); > + > + kvm_sigset_activate(vcpu); > + > + ret = 1; > + run->exit_reason = KVM_EXIT_UNKNOWN; > + while (ret > 0) { > + /* Check conditions before entering the guest */ > + cond_resched(); > + > + kvm_riscv_check_vcpu_requests(vcpu); > + > + preempt_disable(); > + > + local_irq_disable(); > + > + /* > + * Exit if we have a signal pending so that we can deliver > + * the signal to user space. > + */ > + if (signal_pending(current)) { > + ret = -EINTR; > + run->exit_reason = KVM_EXIT_INTR; > + } > + > + /* > + * Ensure we set mode to IN_GUEST_MODE after we disable > + * interrupts and before the final VCPU requests check. > + * See the comment in kvm_vcpu_exiting_guest_mode() and > + * Documentation/virtual/kvm/vcpu-requests.rst > + */ > + vcpu->mode = IN_GUEST_MODE; > + > + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); > + smp_mb__after_srcu_read_unlock(); > + > + if (ret <= 0 || ret can never be == 0 at this point. > + kvm_request_pending(vcpu)) { > + vcpu->mode = OUTSIDE_GUEST_MODE; > + local_irq_enable(); > + preempt_enable(); > + vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); > + continue; > + } > + > + guest_enter_irqoff(); > + > + __kvm_riscv_switch_to(&vcpu->arch); > + > + vcpu->mode = OUTSIDE_GUEST_MODE; > + vcpu->stat.exits++; > + > + /* > + * Save SCAUSE, STVAL, HTVAL, and HTINST because we might > + * get an interrupt between __kvm_riscv_switch_to() and > + * local_irq_enable() which can potentially change CSRs. > + */ > + trap.sepc = 0; > + trap.scause = csr_read(CSR_SCAUSE); > + trap.stval = csr_read(CSR_STVAL); > + trap.htval = csr_read(CSR_HTVAL); > + trap.htinst = csr_read(CSR_HTINST); > + > + /* > + * We may have taken a host interrupt in VS/VU-mode (i.e. > + * while executing the guest). This interrupt is still > + * pending, as we haven't serviced it yet! > + * > + * We're now back in HS-mode with interrupts disabled > + * so enabling the interrupts now will have the effect > + * of taking the interrupt again, in HS-mode this time. > + */ > + local_irq_enable(); > + > + /* > + * We do local_irq_enable() before calling guest_exit() so > + * that if a timer interrupt hits while running the guest > + * we account that tick as being spent in the guest. We > + * enable preemption after calling guest_exit() so that if > + * we get preempted we make sure ticks after that is not > + * counted as guest time. > + */ > + guest_exit(); > + > + preempt_enable(); > + > + vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); > + > + ret = kvm_riscv_vcpu_exit(vcpu, run, &trap); > + } > + > + kvm_sigset_deactivate(vcpu); > + > + vcpu_put(vcpu); > + > + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); > + > + return ret; > +} regards, dan carpenter _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv