From: Bin Meng <bmeng.cn@gmail.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Atish Patra <atish.patra@wdc.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH] riscv: dts: microchip: Define hart clocks
Date: Wed, 16 Jun 2021 14:27:39 +0800 [thread overview]
Message-ID: <20210616062739.398790-1-bmeng.cn@gmail.com> (raw)
From: Bin Meng <bin.meng@windriver.com>
Declare that each hart in the DT is clocked by <&clkcfg 0>.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/,
this adds the same <clock> property to PolarFire SoC CPU nodes so that we can
calculate the running frequency of the hart.
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index a00d9dc560d3..0659068b62f7 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -24,6 +24,7 @@ cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&clkcfg 0>;
status = "disabled";
cpu0_intc: interrupt-controller {
@@ -50,6 +51,7 @@ cpu@1 {
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu1_intc: interrupt-controller {
@@ -76,6 +78,7 @@ cpu@2 {
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu2_intc: interrupt-controller {
@@ -102,6 +105,7 @@ cpu@3 {
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu3_intc: interrupt-controller {
@@ -128,6 +132,7 @@ cpu@4 {
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2021-06-16 6:27 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-16 6:27 Bin Meng [this message]
2021-07-08 13:39 ` [PATCH] riscv: dts: microchip: Define hart clocks Bin Meng
2021-07-13 15:31 ` Conor.Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210616062739.398790-1-bmeng.cn@gmail.com \
--to=bmeng.cn@gmail.com \
--cc=atish.patra@wdc.com \
--cc=bin.meng@windriver.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox