From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To: Kefeng Wang <wangkefeng.wang@huawei.com>
Cc: linux-riscv <linux-riscv@lists.infradead.org>
Subject: Re: [Request for help] issue when add relative extable support to riscv64
Date: Sat, 18 Sep 2021 22:20:48 +0800 [thread overview]
Message-ID: <20210918222048.1e90488e@xhacker> (raw)
In-Reply-To: <7908d27b-1042-61f5-fc8e-f5b00f623b89@huawei.com>
On Sat, 18 Sep 2021 09:23:48 +0800
Kefeng Wang <wangkefeng.wang@huawei.com> wrote:
> On 2021/9/18 0:26, Jisheng Zhang wrote:
> > On Fri, 17 Sep 2021 23:57:33 +0800 Jisheng Zhang wrote:
> >
> >> Hi,
> >>
> >> Now the extable entry contains 16bytes for riscv64 -- 8bytes for the insn and
> >> another 8bytes for the fixup. This wastes mem a bit. I think we can add
> >> the relative extable support. A draft patch put at the end of this mail. But
> >> I met abnormal build errors:
> >>
> >> FATAL: modpost: The relocation at __ex_table+0x0 references
> >> section "__ex_table" which is not executable, IOW
> >> it is not possible for the kernel to fault
> >> at that address. Something is seriously wrong
> >> and should be fixed.
>
> I try this before, and meet the same issue, and add norelax to the label,
>
> but it won't fix the error. seems that we con't find the lable from the
> text?
I also tried adding --no-relax to LDFLAGS and -mno-relax to AFLAGS and CFLAGS
but still met the error. This is an insteresting issue.
Thanks
>
>
> 82 index 1b00badb9f87..cb1aca8e8a23 100644
> 83 --- a/arch/riscv/include/asm/futex.h
> 84 +++ b/arch/riscv/include/asm/futex.h
> 85 @@ -23,17 +23,18 @@
> 86 uintptr_t tmp; \
> 87 __enable_user_access(); \
> 88 __asm__ __volatile__ ( \
> 89 + " .option push \n" \
> 90 + " .option norelax \n" \
> 91 + " .option norvc \n" \
> 92 "1: " insn " \n" \
> 93 + " .option pop \n" \
> 94 "2: \n" \
>
>
>
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next prev parent reply other threads:[~2021-09-18 14:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-17 15:57 [Request for help] issue when add relative extable support to riscv64 Jisheng Zhang
2021-09-17 16:26 ` Jisheng Zhang
2021-09-18 1:23 ` Kefeng Wang
2021-09-18 14:20 ` Jisheng Zhang [this message]
2021-10-10 15:56 ` Jisheng Zhang
2021-10-10 16:59 ` Andreas Schwab
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