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[66.90.148.213]) by smtp.googlemail.com with ESMTPSA id s29sm4236628otg.60.2021.10.06.09.43.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Oct 2021 09:43:34 -0700 (PDT) From: Rob Herring To: Russell King , James Morse , Catalin Marinas , Will Deacon , Guo Ren , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Michael Ellerman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Yoshinori Sato , Rich Felker , x86@kernel.org, Greg Kroah-Hartman Cc: Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, Benjamin Herrenschmidt , Paul Mackerras , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , "Rafael J. Wysocki" , Frank Rowand , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org, openrisc@lists.librecores.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-sh@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Date: Wed, 6 Oct 2021 11:43:20 -0500 Message-Id: <20211006164332.1981454-1-robh@kernel.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211006_094336_904544_8D64FB76 X-CRM114-Status: GOOD ( 12.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The first 10 patches add a new function, of_get_cpu_hwid(), which parses CPU DT node 'reg' property, and then use it to replace all the open coded versions of parsing CPU node 'reg' properties. The last 2 patches add support for populating the cacheinfo 'id' on DT platforms. The minimum associated CPU hwid is used for the id. The id is optional, but necessary for resctrl which is being adapted for Arm MPAM. Tested on arm64. Compile tested on arm, x86 and powerpc. Rob Rob Herring (12): of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes ARM: Use of_get_cpu_hwid() ARM: broadcom: Use of_get_cpu_hwid() arm64: Use of_get_cpu_hwid() csky: Use of_get_cpu_hwid() openrisc: Use of_get_cpu_hwid() powerpc: Use of_get_cpu_hwid() riscv: Use of_get_cpu_hwid() sh: Use of_get_cpu_hwid() x86: dt: Use of_get_cpu_hwid() cacheinfo: Allow for >32-bit cache 'id' cacheinfo: Set cache 'id' based on DT data arch/arm/kernel/devtree.c | 22 ++------------------- arch/arm/mach-bcm/bcm63xx_pmb.c | 6 +++--- arch/arm64/kernel/smp.c | 31 ++---------------------------- arch/csky/kernel/smp.c | 6 ++---- arch/openrisc/kernel/smp.c | 6 +----- arch/powerpc/kernel/smp.c | 7 +------ arch/riscv/kernel/cpu.c | 3 ++- arch/sh/boards/of-generic.c | 5 ++--- arch/x86/kernel/devicetree.c | 5 ++--- drivers/base/cacheinfo.c | 34 ++++++++++++++++++++++++++++++++- drivers/of/base.c | 22 +++++++++++++++++++++ include/linux/cacheinfo.h | 2 +- include/linux/of.h | 1 + 13 files changed, 74 insertions(+), 76 deletions(-) -- 2.30.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv