From: wefu@redhat.com
To: anup.patel@wdc.com, atish.patra@wdc.com,
palmerdabbelt@google.com, guoren@kernel.org,
christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu,
hch@lst.de, liush@allwinnertech.com, wefu@redhat.com,
lazyparser@gmail.com, drew@beagleboard.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
heinrich.schuchardt@canonical.com, gordan.markus@canonical.com,
guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org,
maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com,
andrea.mondelli@huawei.com, behrensj@mit.edu,
xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr,
allen.baum@esperantotech.com, jscheid@ventanamicro.com,
rtrauben@gmail.com, Fu Wei <fu.wei@linaro.org>
Subject: [PATCH 0/2] riscv: Add RISC-V svpbmt extension supports
Date: Wed, 13 Oct 2021 02:33:42 +0800 [thread overview]
Message-ID: <20211012183344.105637-1-wefu@redhat.com> (raw)
From: Fu Wei <fu.wei@linaro.org>
This patch follows the standard pure RISC-V Svpbmt extension in
privilege spec to solve the non-coherent SOC DMA synchronization
issues.
Wei Fu (2):
dt-bindings: riscv: Add mmu-supports with svpbmt
riscv: Add RISC-V svpbmt supports
.../devicetree/bindings/riscv/cpus.yaml | 5 +++
arch/riscv/include/asm/fixmap.h | 2 +-
arch/riscv/include/asm/pgtable-64.h | 8 ++--
arch/riscv/include/asm/pgtable-bits.h | 41 ++++++++++++++++++-
arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++----
arch/riscv/kernel/cpufeature.c | 32 +++++++++++++++
arch/riscv/mm/init.c | 5 +++
7 files changed, 117 insertions(+), 15 deletions(-)
--
2.25.4
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next reply other threads:[~2021-10-12 18:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-12 18:33 wefu [this message]
2021-10-12 18:33 ` [PATCH 1/2] dt-bindings: riscv: Add mmu-supports with svpbmt wefu
2021-10-12 18:33 ` [PATCH 2/2] riscv: Add RISC-V svpbmt extension supports wefu
2021-10-13 3:36 ` [PATCH 0/2] " Guo Ren
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