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Tue, 12 Oct 2021 11:34:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxYV7ys83DL9nO+JaPOB7MrYoWsFwBT15nWiNWaKVgwPs7OrtAs4HQB9269x7iDVWU1Btmyvw== X-Received: by 2002:a63:4743:: with SMTP id w3mr23574406pgk.245.1634063646889; Tue, 12 Oct 2021 11:34:06 -0700 (PDT) Received: from samantha.redhat.com ([209.132.188.80]) by smtp.gmail.com with ESMTPSA id b10sm11617706pfi.122.2021.10.12.11.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 11:34:06 -0700 (PDT) From: wefu@redhat.com To: anup.patel@wdc.com, atish.patra@wdc.com, palmerdabbelt@google.com, guoren@kernel.org, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, hch@lst.de, liush@allwinnertech.com, wefu@redhat.com, lazyparser@gmail.com, drew@beagleboard.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, taiten.peng@canonical.com, aniket.ponkshe@canonical.com, heinrich.schuchardt@canonical.com, gordan.markus@canonical.com, guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, Fu Wei Subject: [PATCH 0/2] riscv: Add RISC-V svpbmt extension supports Date: Wed, 13 Oct 2021 02:33:42 +0800 Message-Id: <20211012183344.105637-1-wefu@redhat.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=wefu@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211012_113412_693380_23E25A1C X-CRM114-Status: UNSURE ( 6.26 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Fu Wei This patch follows the standard pure RISC-V Svpbmt extension in privilege spec to solve the non-coherent SOC DMA synchronization issues. Wei Fu (2): dt-bindings: riscv: Add mmu-supports with svpbmt riscv: Add RISC-V svpbmt supports .../devicetree/bindings/riscv/cpus.yaml | 5 +++ arch/riscv/include/asm/fixmap.h | 2 +- arch/riscv/include/asm/pgtable-64.h | 8 ++-- arch/riscv/include/asm/pgtable-bits.h | 41 ++++++++++++++++++- arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++---- arch/riscv/kernel/cpufeature.c | 32 +++++++++++++++ arch/riscv/mm/init.c | 5 +++ 7 files changed, 117 insertions(+), 15 deletions(-) -- 2.25.4 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv