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Tue, 12 Oct 2021 11:34:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuhdPj8LMwjOhpOZoKPlUbm6hkFroKNtw/F5RLD4p3o4kgtU+iDfWu7RevbajN7vmCUgI5rg== X-Received: by 2002:a63:2b12:: with SMTP id r18mr23683880pgr.256.1634063658052; Tue, 12 Oct 2021 11:34:18 -0700 (PDT) Received: from samantha.redhat.com ([209.132.188.80]) by smtp.gmail.com with ESMTPSA id b10sm11617706pfi.122.2021.10.12.11.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 11:34:17 -0700 (PDT) From: wefu@redhat.com To: anup.patel@wdc.com, atish.patra@wdc.com, palmerdabbelt@google.com, guoren@kernel.org, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, hch@lst.de, liush@allwinnertech.com, wefu@redhat.com, lazyparser@gmail.com, drew@beagleboard.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, taiten.peng@canonical.com, aniket.ponkshe@canonical.com, heinrich.schuchardt@canonical.com, gordan.markus@canonical.com, guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, Anup Patel , Palmer Dabbelt , Rob Herring Subject: [PATCH 1/2] dt-bindings: riscv: Add mmu-supports with svpbmt Date: Wed, 13 Oct 2021 02:33:43 +0800 Message-Id: <20211012183344.105637-2-wefu@redhat.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20211012183344.105637-1-wefu@redhat.com> References: <20211012183344.105637-1-wefu@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=wefu@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211012_113422_362975_A8405FA1 X-CRM114-Status: UNSURE ( 8.16 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Wei Fu Previous patch has added svpbmt in arch/riscv and changed the DT mmu-type. Update dt-bindings related property here. Signed-off-by: Wei Fu Co-developed-by: Guo Ren Signed-off-by: Guo Ren Cc: Anup Patel Cc: Palmer Dabbelt Cc: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e534f6a7cfa1..c481c110d391 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -59,6 +59,11 @@ properties: - riscv,sv48 - riscv,none + mmu-supports-svpbmt: + description: + Describes the CPU's mmu-supports-svpbmt support + $ref: '/schemas/types.yaml#/definitions/phandle' + riscv,isa: description: Identifies the specific RISC-V instruction set architecture -- 2.25.4 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv