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From: Nikita Shubin <nikita.shubin@maquefel.me>
To: "João Mário Domingos" <joao.mario@tecnico.ulisboa.pt>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
	aou@eecs.berkeley.edu, atish.patra@wdc.com, anup.patel@wdc.com,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events
Date: Tue, 23 Nov 2021 08:19:51 +0300	[thread overview]
Message-ID: <20211123081951.441e50e4@redslave.neermore.group> (raw)
In-Reply-To: <20211122152408.GB10739@joaomariovmubuntu>

Hello Mario!

On Mon, 22 Nov 2021 15:24:08 +0000
João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:

> On Wed, Nov 17, 2021 at 02:25:39PM +0300, Nikita Shubin wrote:
> > On Tue, 16 Nov 2021 15:48:12 +0000
> > João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> > 
> > Hello Mario!
> >   
> Hello Nikita!
> > > +  {
> > > +    "EventName": "UTLB_MISS",
> > > +    "EventCode": "0x0002002",
> > > +    "BriefDescription": "UTLB miss"
> > > +  }  
> > 
> > I don't see such thing in FU740 v1p3 manual - am i missing
> > something ?  
> You are absolutelly right, there is no reference to the L2 cache
> (Unified Cache) TLB misses event in the FU740 v1p3 manual. But
> considering that the FU740 is composed of 1 S7 and 4 U74 cores, I
> used the U74 core complex manual
> [https://www.starfivetech.com/uploads/u74_core_complex_manual_21G1.pdf]
> as the source for events. Did you test the utlb_miss event, and does
> it work in your board?

Thank you for pointing this out, it works indeed. Unfortunately not the
first inexactness in the FU740 v1p3 manual.

> 
> Best,
> João Mário
> > 
> > Yours,
> > Nikita Shubin
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv  


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  reply	other threads:[~2021-11-23  5:22 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-09 10:25 [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched João Mário Domingos
2021-11-09 10:25 ` [PATCH 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
2021-11-15  8:23   ` Nikita Shubin
2021-11-16 15:54     ` João Mário Domingos
2021-11-09 10:25 ` [PATCH 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
2021-11-09 10:25 ` [PATCH 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
2021-11-09 10:25 ` [PATCH 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
2021-11-10 13:55 ` [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
2021-11-16 15:48   ` [PATCH v2 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
2021-11-16 15:48   ` [PATCH v2 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
2021-11-16 15:48   ` [PATCH v2 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
2021-11-16 15:48   ` [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
2021-11-17 11:25     ` Nikita Shubin
2021-11-22 15:24       ` João Mário Domingos
2021-11-23  5:19         ` Nikita Shubin [this message]
2021-11-17 12:25   ` [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
2021-11-18  8:00     ` Atish Patra
2021-11-22 14:57       ` João Mário Domingos
2021-11-22 16:26         ` Jessica Clarke
2021-11-22 21:17           ` Atish Patra
2021-11-23 17:39             ` João Mário Domingos
2021-11-23  5:24         ` Nikita Shubin

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