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From: Nikita Shubin <nikita.shubin@maquefel.me>
To: "João Mário Domingos" <joao.mario@tecnico.ulisboa.pt>
Cc: Atish Patra <atishp@atishpatra.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Atish Patra <atish.patra@wdc.com>,
	Anup Patel <anup.patel@wdc.com>,
	linux-riscv <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched
Date: Tue, 23 Nov 2021 08:24:56 +0300	[thread overview]
Message-ID: <20211123082456.003778f6@redslave.neermore.group> (raw)
In-Reply-To: <20211122145751.GA10739@joaomariovmubuntu>

Hello Mario!

On Mon, 22 Nov 2021 14:57:52 +0000
João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> 
> As the changes to the U-Boot are short I'm including them here,
> please tell me if I should include them in other way. I merged my
> changes with Atish's own patch to simplify the process.
> 
> diff -u b/arch/riscv/dts/fu740-c000.dtsi
> b/arch/riscv/dts/fu740-c000.dtsi --- b/arch/riscv/dts/fu740-c000.dtsi
> +++ b/arch/riscv/dts/fu740-c000.dtsi
> @@ -141,6 +141,49 @@
>                 #size-cells = <2>;
>                 compatible = "sifive,fu740-c000", "sifive,fu740",
> "simple-bus"; ranges;
> +               pmu {
> +                       compatible = "riscv,pmu";
> +                       pmu,raw-event-to-mhpmcounters = <0x00000000
> 0x00000100 0x18
> +                                                       0x00000000
> 0x00000200 0x18
> +                                                       0x00000000
> 0x00000400 0x18
> +                                                       0x00000000
> 0x00000800 0x18
> +                                                       0x00000000
> 0x00001000 0x18
> +                                                       0x00000000
> 0x00002000 0x18
> +                                                       0x00000000
> 0x00004000 0x18
> +                                                       0x00000000
> 0x00008000 0x18
> +                                                       0x00000000
> 0x00010000 0x18
> +                                                       0x00000000
> 0x00020000 0x18
> +                                                       0x00000000
> 0x00040000 0x18
> +                                                       0x00000000
> 0x00080000 0x18
> +                                                       0x00000000
> 0x00100000 0x18
> +                                                       0x00000000
> 0x00200000 0x18
> +                                                       0x00000000
> 0x00400000 0x18
> +                                                       0x00000000
> 0x00800000 0x18
> +                                                       0x00000000
> 0x01000000 0x18
> +                                                       0x00000000
> 0x02000000 0x18
> +                                                       0x00000000
> 0x00000101 0x18
> +                                                       0x00000000
> 0x00000201 0x18
> +                                                       0x00000000
> 0x00000401 0x18
> +                                                       0x00000000
> 0x00000801 0x18
> +                                                       0x00000000
> 0x00001001 0x18
> +                                                       0x00000000
> 0x00002001 0x18
> +                                                       0x00000000
> 0x00004001 0x18
> +                                                       0x00000000
> 0x00008001 0x18
> +                                                       0x00000000
> 0x00010001 0x18
> +                                                       0x00000000
> 0x00020001 0x18
> +                                                       0x00000000
> 0x00040001 0x18
> +                                                       0x00000000
> 0x00000102 0x18
> +                                                       0x00000000
> 0x00000202 0x18
> +                                                       0x00000000
> 0x00000402 0x18
> +                                                       0x00000000
> 0x00000802 0x18
> +                                                       0x00000000
> 0x00001002 0x18
> +                                                       0x00000000
> 0x00002002 0x18>;
> +                       pmu,event-to-mhpmcounters = <0x05 0x06 0x18
> +                                                    0x10009 0x10009
> 0x18>;
> +                       pmu,event-to-mhpmevent = <0x05 0x00000000
> 0x4000
> +                                                 0x06 0x00000000
> 0x4001
> +                                                 0x10008 0x00000000
> 0x102>;
> +               };

Well, i definitely thought it was shorter...

After applying Vincent Chen patches:
https://patchwork.ozlabs.org/project/opensbi/patch/20211110050153.26935-1-vincent.chen@sifive.com/

My looks like:

diff --git a/arch/riscv/dts/fu740-c000.dtsi
b/arch/riscv/dts/fu740-c000.dtsi index 649efe400a..6a155b2b86 100644
--- a/arch/riscv/dts/fu740-c000.dtsi
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -141,6 +141,17 @@
                #size-cells = <2>;
                compatible = "sifive,fu740-c000", "sifive,fu740",
"simple-bus"; ranges;
+               pmu {
+                       compatible = "riscv,pmu";
+                       riscv,raw-event-to-mhpmcounters = <0x00000000
0x3ffff00 0x0 0x0 0x18
+                                                        0x00000000
0x7ff01 0x0 0x1 0x18
+                                                        0x00000000
0x3f02 0x0 0x2 0x18>;
+                       riscv,event-to-mhpmcounters = <0x05 0x06 0x18
+                                                    0x10009 0x10009
0x18>;
+                       riscv,event-to-mhpmevent = <0x05 0x00000000
0x4000
+                                                 0x06 0x00000000 0x4001
+                                                 0x10008 0x00000000
0x102>;
+               };
                plic0: interrupt-controller@c000000 {
                        #interrupt-cells = <1>;
                        compatible = "sifive,plic-1.0.0";

Shorter indeed, but surely less readable.




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      parent reply	other threads:[~2021-11-23  5:25 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-09 10:25 [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched João Mário Domingos
2021-11-09 10:25 ` [PATCH 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
2021-11-15  8:23   ` Nikita Shubin
2021-11-16 15:54     ` João Mário Domingos
2021-11-09 10:25 ` [PATCH 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
2021-11-09 10:25 ` [PATCH 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
2021-11-09 10:25 ` [PATCH 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
2021-11-10 13:55 ` [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
2021-11-16 15:48   ` [PATCH v2 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
2021-11-16 15:48   ` [PATCH v2 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
2021-11-16 15:48   ` [PATCH v2 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
2021-11-16 15:48   ` [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
2021-11-17 11:25     ` Nikita Shubin
2021-11-22 15:24       ` João Mário Domingos
2021-11-23  5:19         ` Nikita Shubin
2021-11-17 12:25   ` [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
2021-11-18  8:00     ` Atish Patra
2021-11-22 14:57       ` João Mário Domingos
2021-11-22 16:26         ` Jessica Clarke
2021-11-22 21:17           ` Atish Patra
2021-11-23 17:39             ` João Mário Domingos
2021-11-23  5:24         ` Nikita Shubin [this message]

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