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Sun, 28 Nov 2021 17:40:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJzfqf9/+YWzUdcEIBNa1uk2fXxWr4qKG4LaM8zDp5rwntZetIY4fp+YtWSMVpTRzNqF/xMX/g== X-Received: by 2002:a17:90a:db02:: with SMTP id g2mr35017297pjv.76.1638150042296; Sun, 28 Nov 2021 17:40:42 -0800 (PST) Received: from samantha.redhat.com ([209.132.188.80]) by smtp.gmail.com with ESMTPSA id e18sm10367575pgl.50.2021.11.28.17.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Nov 2021 17:40:41 -0800 (PST) From: wefu@redhat.com To: anup.patel@wdc.com, atishp04@gmail.com, palmer@dabbelt.com, guoren@kernel.org, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, hch@lst.de, liush@allwinnertech.com, wefu@redhat.com, lazyparser@gmail.com, drew@beagleboard.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, taiten.peng@canonical.com, aniket.ponkshe@canonical.com, heinrich.schuchardt@canonical.com, gordan.markus@canonical.com, guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, Anup Patel , Rob Herring Subject: [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt Date: Mon, 29 Nov 2021 09:40:06 +0800 Message-Id: <20211129014007.286478-2-wefu@redhat.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20211129014007.286478-1-wefu@redhat.com> References: <20211129014007.286478-1-wefu@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=wefu@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211128_174048_042402_44BF2451 X-CRM114-Status: UNSURE ( 8.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Wei Fu Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt" in the DT mmu node. Update dt-bindings related property here. Signed-off-by: Wei Fu Co-developed-by: Guo Ren Signed-off-by: Guo Ren Cc: Anup Patel Cc: Palmer Dabbelt Cc: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index aa5fb64d57eb..9ff9cbdd8a85 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -63,6 +63,16 @@ properties: - riscv,sv48 - riscv,none + mmu: + description: + Describes the CPU's MMU Standard Extensions support. + These values originate from the RISC-V Privileged + Specification document, available from + https://riscv.org/specifications/ + $ref: '/schemas/types.yaml#/definitions/string' + enum: + - riscv,svpmbt + riscv,isa: description: Identifies the specific RISC-V instruction set architecture -- 2.25.4 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv