From: Christoph Hellwig <hch@lst.de>
To: Heiko Stuebner <heiko@sntech.de>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, wefu@redhat.com, liush@allwinnertech.com,
guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org,
drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org,
maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com,
andrea.mondelli@huawei.com, behrensj@mit.edu,
xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr,
allen.baum@esperantotech.com, jscheid@ventanamicro.com,
rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu
Subject: Re: [PATCH v5 00/14] riscv: support for svpbmt and D1 memory types
Date: Mon, 24 Jan 2022 08:22:08 +0100 [thread overview]
Message-ID: <20220124072208.GA21441@lst.de> (raw)
In-Reply-To: <20220121163618.351934-1-heiko@sntech.de>
On Fri, Jan 21, 2022 at 05:36:04PM +0100, Heiko Stuebner wrote:
> So this is my try at implementing svpbmt (and the diverging D1 memory
> types using the alternatives framework).
Please spell out what it does. While I can remember the original single
letter extensions very well, the new priviliged extension naming is
just letter salad.
You might also want to explain in more detail what it does and why you
want to support it.
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prev parent reply other threads:[~2022-01-24 7:22 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-21 16:36 [PATCH v5 00/14] riscv: support for svpbmt and D1 memory types Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 01/14] riscv: only use IPIs to handle cache-flushes on remote cpus Heiko Stuebner
2022-01-22 3:45 ` Atish Patra
2022-01-24 12:30 ` Heiko Stübner
2022-01-22 4:10 ` Anup Patel
2022-01-21 16:36 ` [PATCH v5 02/14] riscv: integrate alternatives better into the main architecture Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 03/14] riscv: allow different stages with alternatives Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 04/14] riscv: implement module alternatives Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 05/14] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 06/14] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 07/14] riscv: prevent compressed instructions in alternatives Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 08/14] riscv: move boot alternatives to a slightly earlier position Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 10/14] riscv: add cpufeature handling via alternatives Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 11/14] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt Heiko Stuebner
2022-02-04 22:33 ` Rob Herring
2022-02-07 13:39 ` Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 12/14] riscv: add RISC-V Svpbmt extension supports Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 13/14] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner
2022-01-21 16:36 ` [PATCH v5 14/14] riscv: add memory-type errata for T-Head Heiko Stuebner
2022-01-24 7:22 ` Christoph Hellwig [this message]
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