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From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	Damien Le Moal <damien.lemoal@wdc.com>,
	devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>
Subject: [PATCH v3 5/6] RISC-V: Do no continue isa string parsing without correct XLEN
Date: Tue, 15 Feb 2022 01:02:10 -0800	[thread overview]
Message-ID: <20220215090211.911366-6-atishp@rivosinc.com> (raw)
In-Reply-To: <20220215090211.911366-1-atishp@rivosinc.com>

The isa string should begin with either rv64 or rv32. Otherwise, it is
an incorrect isa string. Currently, the string parsing continues even if
it doesnot begin with current XLEN.

Fix this by checking if it found "rv64" or "rv32" in the beginning.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kernel/cpufeature.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index af9a57ad3d4e..0c818035ec92 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
 	for_each_of_cpu_node(node) {
 		unsigned long this_hwcap = 0;
 		uint64_t this_isa = 0;
+		const char *temp;
 
 		if (riscv_of_processor_hartid(node) < 0)
 			continue;
@@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
 			continue;
 		}
 
+		temp = isa;
 #if IS_ENABLED(CONFIG_32BIT)
 		if (!strncmp(isa, "rv32", 4))
 			isa += 4;
@@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void)
 		if (!strncmp(isa, "rv64", 4))
 			isa += 4;
 #endif
+		/* The riscv,isa DT property must start with rv64 or rv32 */
+		if (temp == isa)
+			continue;
 		for (; *isa; ++isa) {
 			const char *ext = isa++;
 			const char *ext_end = isa;
-- 
2.30.2


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  parent reply	other threads:[~2022-02-15  9:03 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-15  9:02 [PATCH v3 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-02-15  9:02 ` [PATCH v3 1/6] RISC-V: Correctly print supported extensions Atish Patra
2022-02-15  9:41   ` Anup Patel
2022-02-15  9:02 ` [PATCH v3 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
2022-02-15  9:02 ` [PATCH v3 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra
2022-02-15 10:14   ` Anup Patel
2022-02-15  9:02 ` [PATCH v3 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
2022-02-15 10:23   ` Anup Patel
2022-02-15 23:11     ` Atish Patra
2022-02-15  9:02 ` Atish Patra [this message]
2022-02-15  9:02 ` [PATCH v3 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
2022-02-15 15:56 ` [PATCH v3 0/6] Provide a fraemework for RISC-V " Jisheng Zhang
2022-02-15 19:06   ` Atish Kumar Patra
2022-03-26  7:18     ` Jisheng Zhang

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