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From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	Damien Le Moal <damien.lemoal@wdc.com>,
	devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>
Subject: [RFC PATCH v2 1/7] RISC-V: Add SSTC extension CSR details
Date: Fri,  4 Mar 2022 12:10:14 -0800	[thread overview]
Message-ID: <20220304201020.810380-2-atishp@rivosinc.com> (raw)
In-Reply-To: <20220304201020.810380-1-atishp@rivosinc.com>

This patch just introduces the required CSR fields related to the
SSTC extension.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/include/asm/csr.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index ae711692eec9..8f37c063a205 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -165,6 +165,9 @@
 #define CSR_SIP			0x144
 #define CSR_SATP		0x180
 
+#define CSR_STIMECMP		0x14D
+#define CSR_STIMECMPH		0x15D
+
 #define CSR_VSSTATUS		0x200
 #define CSR_VSIE		0x204
 #define CSR_VSTVEC		0x205
@@ -174,6 +177,8 @@
 #define CSR_VSTVAL		0x243
 #define CSR_VSIP		0x244
 #define CSR_VSATP		0x280
+#define CSR_VSTIMECMP		0x24D
+#define CSR_VSTIMECMPH		0x25D
 
 #define CSR_HSTATUS		0x600
 #define CSR_HEDELEG		0x602
@@ -189,6 +194,8 @@
 #define CSR_HTINST		0x64a
 #define CSR_HGATP		0x680
 #define CSR_HGEIP		0xe12
+#define CSR_HENVCFG		0x60A
+#define CSR_HENVCFGH		0x61A
 
 #define CSR_MSTATUS		0x300
 #define CSR_MISA		0x301
@@ -247,6 +254,10 @@
 #define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
 #define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)
 
+/* ENVCFG related bits */
+#define HENVCFG_STCE	63
+#define HENVCFGH_STCE	31
+
 #ifndef __ASSEMBLY__
 
 #define csr_swap(csr, val)					\
-- 
2.30.2


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  reply	other threads:[~2022-03-04 20:11 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-04 20:10 [RFC PATCH v2 0/7] Add Sstc extension support Atish Patra
2022-03-04 20:10 ` Atish Patra [this message]
2022-03-04 20:10 ` [RFC PATCH v2 2/7] RISC-V: Enable sstc extension parsing from DT Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 3/7] RISC-V: Prefer sstc extension if available Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 4/7] RISC-V: KVM: Remove 's' & 'u' as valid ISA extension Atish Patra
2022-03-18  3:25   ` Anup Patel
2022-03-04 20:10 ` [RFC PATCH v2 5/7] RISC-V: KVM: Restrict the extensions that can be disabled Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 6/7] RISC-V: KVM: Introduce ISA extension register Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 7/7] RISC-V: KVM: Support sstc extension Atish Patra
2022-03-04 20:38   ` Jessica Clarke
2022-03-05  9:37     ` Atish Patra

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