From: <conor.dooley@microchip.com>
To: <mpm@selenic.com>, <herbert@gondor.apana.org.au>
Cc: <lewis.hanly@microchip.com>, <linux-kernel@vger.kernel.org>,
<linux-crypto@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
"Conor Dooley" <conor.dooley@microchip.com>
Subject: [PATCH 0/2] Add support for hwrng on PolarFire SoC
Date: Mon, 7 Mar 2022 15:40:22 +0000 [thread overview]
Message-ID: <20220307154023.813158-1-conor.dooley@microchip.com> (raw)
From: Conor Dooley <conor.dooley@microchip.com>
As it says on the tin, add support for the hardware rng on PolarFire
SoC, which is accessed via the system controller. While we're at it,
add the rng driver to the list of files included as part of the SoC
support in MAINTAINERS.
Base commit is in arm/soc branch of the soc tree as the hwrng driver
depends on the system controller, which is to be introduced via that
tree in 5.18
Conor Dooley (2):
hwrng: mpfs - add polarfire soc hwrng support
MAINTAINERS: update PolarFire SoC support
MAINTAINERS | 1 +
drivers/char/hw_random/Kconfig | 13 ++++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/mpfs-rng.c | 103 ++++++++++++++++++++++++++++++
4 files changed, 118 insertions(+)
create mode 100644 drivers/char/hw_random/mpfs-rng.c
base-commit: a483b1b232e616d0095a59b987ffc739bc1b56bc
--
2.35.1
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next reply other threads:[~2022-03-07 15:37 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-07 15:40 conor.dooley [this message]
2022-03-07 15:40 ` [PATCH 1/2] hwrng: mpfs - add polarfire soc hwrng support conor.dooley
2022-03-08 7:55 ` Dominik Brodowski
2022-03-09 8:09 ` Conor.Dooley
2022-03-07 15:40 ` [PATCH 2/2] MAINTAINERS: update PolarFire SoC support conor.dooley
2022-03-18 12:33 ` [PATCH 0/2] Add support for hwrng on PolarFire SoC Conor Dooley
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