[RFC PATCH v2 0/2] Risc-V Svinval support

From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
	Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org
Subject: [RFC PATCH v2 0/2] Risc-V Svinval support
Date: Sun, 24 Apr 2022 14:32:14 +0530	[thread overview]
Message-ID: <20220424090216.21887-1-mchitale@ventanamicro.com> (raw)

This patch adds support for the Svinval extension as defined in the
Risc V Privileged specification. This patchset depends on:

https://patchwork.kernel.org/project/linux-riscv/list/?series=632984

The feature was tested with qemu from latest master branch with
following additional patch:
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00142.html

Changes in V2:

- Rebased on 5.18-rc3
- update riscv_fill_hwcap to probe Svinval extension

Mayuresh Chitale (2):
  riscv: enum for svinval extension
  riscv: mm: use svinval instructions instead of sfence.vma

 arch/riscv/include/asm/hwcap.h    |   1 +
 arch/riscv/include/asm/tlbflush.h |  12 ++++
 arch/riscv/kernel/cpu.c           |   1 +
 arch/riscv/kernel/cpufeature.c    |   1 +
 arch/riscv/kernel/setup.c         |   1 +
 arch/riscv/mm/tlbflush.c          | 116 ++++++++++++++++++++++++++++--
 6 files changed, 126 insertions(+), 6 deletions(-)

-- 
2.17.1

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