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Thu, 26 May 2022 03:14:00 -0700 (PDT) Date: Thu, 26 May 2022 15:43:54 +0530 From: Sunil V L To: Heinrich Schuchardt Cc: Ard Biesheuvel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Atish Patra , Anup Patel , linux-riscv , Linux Kernel Mailing List , linux-efi , Sunil V L Subject: Re: [PATCH 5/5] riscv/efi_stub: Support for 64bit boot-hartid Message-ID: <20220526101354.GA19431@sunil-laptop> References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> <20220525151106.2176147-6-sunilvl@ventanamicro.com> <1e90b15b-8c73-0de8-2885-1292923b7575@canonical.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1e90b15b-8c73-0de8-2885-1292923b7575@canonical.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220526_031403_691397_5FEBCBBD X-CRM114-Status: GOOD ( 26.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, May 25, 2022 at 06:09:05PM +0200, Heinrich Schuchardt wrote: > On 5/25/22 17:48, Ard Biesheuvel wrote: > > On Wed, 25 May 2022 at 17:11, Sunil V L wrote: > > > > > > The boot-hartid can be a 64bit value on RV64 platforms. Currently, > > > the "boot-hartid" in DT is assumed to be 32bit only. This patch > > > detects the size of the "boot-hartid" and uses 32bit or 64bit > > > FDT reads appropriately. > > > > > > Signed-off-by: Sunil V L > > > --- > > > drivers/firmware/efi/libstub/riscv-stub.c | 12 +++++++++--- > > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/firmware/efi/libstub/riscv-stub.c b/drivers/firmware/efi/libstub/riscv-stub.c > > > index 9e85e58d1f27..d748533f1329 100644 > > > --- a/drivers/firmware/efi/libstub/riscv-stub.c > > > +++ b/drivers/firmware/efi/libstub/riscv-stub.c > > > @@ -29,7 +29,7 @@ static int get_boot_hartid_from_fdt(void) > > > { > > > const void *fdt; > > > int chosen_node, len; > > > - const fdt32_t *prop; > > > + const void *prop; > > > > > > fdt = get_efi_config_table(DEVICE_TREE_GUID); > > > if (!fdt) > > > @@ -40,10 +40,16 @@ static int get_boot_hartid_from_fdt(void) > > > return -EINVAL; > > > > > > prop = fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); > > > - if (!prop || len != sizeof(u32)) > > > + if (!prop) > > > + return -EINVAL; > > > + > > > + if (len == sizeof(u32)) > > > + hartid = (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); > > > + else if (len == sizeof(u64)) > > > + hartid = (unsigned long) fdt64_to_cpu(*(fdt64_t *)prop); > > > > Does RISC-V care about alignment? A 64-bit quantity is not guaranteed > > to appear 64-bit aligned in the DT, and the cast violates C alignment > > rules, so this should probably used get_unaligned_be64() or something > > like that. > > When running in S-mode the SBI handles unaligned access but this has a > performance penalty. > > We could use fdt64_to_cpu(__get_unaligned_t(fdt64_t, prop)) here. Thank you very much for the feedback. Have updated as per your suggestion and sent V2. Thanks Sunil > > Best regards > > Heinrich > > > > > > > > + else > > > return -EINVAL; > > > > > > - hartid = fdt32_to_cpu(*prop); > > > return 0; > > > } > > > > > > -- > > > 2.25.1 > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv