From: Conor Dooley <conor.dooley@microchip.com>
To: Mark Brown <broonie@kernel.org>
Cc: Daire McNamara <daire.mcnamara@microchip.com>,
<linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>,
<linux-riscv@lists.infradead.org>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH 2/2] MAINTAINERS: add spi to PolarFire SoC entry
Date: Tue, 7 Jun 2022 08:38:34 +0100 [thread overview]
Message-ID: <20220607073833.2331539-3-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220607073833.2331539-1-conor.dooley@microchip.com>
Add the newly introduced spi driver to the existing PolarFire SoC entry.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f468864fd268..279a25065942 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16955,6 +16955,7 @@ S: Supported
F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/soc/microchip/
+F: drivers/spi/spi-microchip-core.c
F: include/soc/microchip/mpfs.h
RNBD BLOCK DRIVERS
--
2.36.1
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next prev parent reply other threads:[~2022-06-07 7:41 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-07 7:38 [PATCH 0/2] Add support for PolarFire SoC's spi controllers Conor Dooley
2022-06-07 7:38 ` [PATCH 1/2] spi: add support for microchip fpga " Conor Dooley
2022-06-07 7:38 ` Conor Dooley [this message]
2022-06-07 17:33 ` [PATCH 0/2] Add support for PolarFire SoC's " Mark Brown
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