[PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu

Anup Patel
2022-07-27T11:44:13Z

We add an optional DT property riscv,timer-can-wake-cpu which if present
in CPU DT node then CPU timer is always powered-on and never loses context.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..b60b64b4113a 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -78,6 +78,12 @@ properties:
- rv64imac
- rv64imafdc

+ riscv,timer-can-wake-cpu:
+ type: boolean
+ description:
+ If present, the timer interrupt can wake up the CPU from
+ suspend/idle state.
+
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false

--
2.34.1