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Thu, 18 Aug 2022 08:06:47 -0700 (PDT) Received: from robh.at.kernel.org ([2607:fb90:5fe0:b4f5:6e22:4704:df60:73a3]) by smtp.gmail.com with ESMTPSA id dt2-20020a05620a478200b006bb024c5021sm1755015qkb.25.2022.08.18.08.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 08:06:47 -0700 (PDT) Received: (nullmailer pid 1870414 invoked by uid 1000); Thu, 18 Aug 2022 15:06:45 -0000 Date: Thu, 18 Aug 2022 09:06:44 -0600 From: Rob Herring To: Conor Dooley Cc: Daire McNamara , Bjorn Helgaas , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 2/6] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties Message-ID: <20220818150644.GJ1829017-robh@kernel.org> References: <20220816182547.3454843-1-mail@conchuod.ie> <20220816182547.3454843-3-mail@conchuod.ie> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220816182547.3454843-3-mail@conchuod.ie> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220818_080649_742171_4C4F0CDA X-CRM114-Status: GOOD ( 21.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Aug 16, 2022 at 07:25:44PM +0100, Conor Dooley wrote: > From: Conor Dooley > > Recent versions of dt-schema warn about unevaluatedProperties: > arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected) > From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > > The clocks are required to enable interfaces between the FPGA fabric > and the core complex, so add them to the binding. > > Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") > Signed-off-by: Conor Dooley > --- > dt-schema v2022.08 is required to replicate > --- > .../bindings/pci/microchip,pcie-host.yaml | 25 +++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > index edb4f81253c8..6bbde8693ef8 100644 > --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > @@ -25,6 +25,31 @@ properties: > - const: cfg > - const: apb > > + clocks: > + description: > + Fabric Interface Controllers, FICs, are the interface between the FPGA > + fabric and the core complex on PolarFire SoC. The FICs require two clocks, > + one from each side of the interface. The "FIC clocks" described by this > + property are on the core complex side & communication through a FIC is not > + possible unless it's corresponding clock is enabled. A clock must be > + enabled for each of the interfaces the root port is connected through. > + This could in theory be all 4 interfaces, one interface or any combination > + in between. > + minItems: 1 > + items: > + - description: FIC0's clock > + - description: FIC1's clock > + - description: FIC2's clock > + - description: FIC3's clock > + > + clock-names: > + description: > + As any FIC connection combination is possible, the names should match the > + order in the clocks property and take the form "ficN" where N is a number > + 0-3 > + minItems: 1 > + maxItems: 4 items: pattern: '^fic[0-3]$' > + > interrupts: > minItems: 1 > items: > -- > 2.37.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv