From: Andrew Jones <ajones@ventanamicro.com>
To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org,
mchitale@ventanamicro.com, heiko@sntech.de
Subject: [PATCH 1/4] riscv: Add X register names to gpr-nums
Date: Fri, 19 Aug 2022 16:02:47 +0200 [thread overview]
Message-ID: <20220819140250.3892995-2-ajones@ventanamicro.com> (raw)
In-Reply-To: <20220819140250.3892995-1-ajones@ventanamicro.com>
When encoding instructions it's sometimes necessary to set a
register field to a precise number. This is easiest to do using
the x<num> naming.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/gpr-num.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/gpr-num.h b/arch/riscv/include/asm/gpr-num.h
index dfee2829fc7c..efeb5edf8a3a 100644
--- a/arch/riscv/include/asm/gpr-num.h
+++ b/arch/riscv/include/asm/gpr-num.h
@@ -3,6 +3,11 @@
#define __ASM_GPR_NUM_H
#ifdef __ASSEMBLY__
+
+ .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+ .equ .L__gpr_num_x\num, \num
+ .endr
+
.equ .L__gpr_num_zero, 0
.equ .L__gpr_num_ra, 1
.equ .L__gpr_num_sp, 2
@@ -39,6 +44,9 @@
#else /* __ASSEMBLY__ */
#define __DEFINE_ASM_GPR_NUMS \
+" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31\n" \
+" .equ .L__gpr_num_x\\num, \\num\n" \
+" .endr\n" \
" .equ .L__gpr_num_zero, 0\n" \
" .equ .L__gpr_num_ra, 1\n" \
" .equ .L__gpr_num_sp, 2\n" \
--
2.37.1
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next prev parent reply other threads:[~2022-08-19 14:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-19 14:02 [PATCH 0/4] riscv: Introduce support for defining instructions Andrew Jones
2022-08-19 14:02 ` Andrew Jones [this message]
2022-08-29 8:24 ` [PATCH 1/4] riscv: Add X register names to gpr-nums Anup Patel
2022-08-19 14:02 ` [PATCH 2/4] riscv: Introduce support for defining instructions Andrew Jones
2022-08-19 14:26 ` Andrew Jones
2022-08-29 8:31 ` Anup Patel
2022-08-19 14:02 ` [PATCH 3/4] riscv: KVM: Apply insn-def to hfence encodings Andrew Jones
2022-08-29 8:37 ` Anup Patel
2022-08-29 9:47 ` Andrew Jones
2022-08-30 3:12 ` Anup Patel
2022-08-19 14:02 ` [PATCH 4/4] riscv: KVM: Apply insn-def to hlv encodings Andrew Jones
2022-08-29 8:44 ` Anup Patel
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