[PATCH v1 2/4] riscv: dts: microchip: add fabric address translation properties

daire.mcnamara
2022-09-02T14:22:56Z

From: Daire McNamara <daire.mcnamara@microchip.com>

On PolarFire SoC both in- & out-bound address translations occur in two
stages. The specific translations are tightly coupled to the FPGA
designs and supplement the {dma-,}ranges properties. The first stage of
the translation is done by the FPGA fabric & the second by the root
port.
Add outbound address translation information so that the translation
tables in the root port's bridge layer can be configured to account for
the translation done by the FPGA fabric on Icicle Kit reference design.

Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 98f04be0dc6b..6839650e7d1b 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -57,7 +57,11 @@ pcie: pcie@3000000000 {
interrupt-map-mask = <0 0 0 7>;
clocks = <&fabric_clk1>, <&fabric_clk3>;
clock-names = "fic1", "fic3";
- ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
+ ranges = <0x0000000 0x0 0x0000000 0x30 0x0000000 0x0 0x8000000>,
+ <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
+ microchip,outbound-fabric-translation-ranges =
+ <0x0000000 0x0 0x0000000 0x30 0x0000000 0x0 0x8000000>,
+ <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
msi-parent = <&pcie>;
msi-controller;
--
2.25.1