* [PATCH v1] RISC-V: KVM: Allow Guest use Zihintpause extension
@ 2022-09-15 15:29 Mayuresh Chitale
0 siblings, 0 replies; 5+ messages in thread
From: Mayuresh Chitale @ 2022-09-15 15:29 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou
Cc: Mayuresh Chitale, Atish Patra, Anup Patel, linux-riscv
We should advertise Zihintpause ISA extension to KVM user-space whenever
host supports it. This will allow KVM user-space (i.e. QEMU or KVMTOOL)
to pass on this information to Guest via ISA string.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index b6770ee08872..9085b90cf324 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_SVPBMT,
KVM_RISCV_ISA_EXT_SSTC,
KVM_RISCV_ISA_EXT_SVINVAL,
+ KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 901bb5c0cb50..0de0dd22e734 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
RISCV_ISA_EXT_SVPBMT,
RISCV_ISA_EXT_SSTC,
RISCV_ISA_EXT_SVINVAL,
+ RISCV_ISA_EXT_ZIHINTPAUSE,
};
static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_M:
case KVM_RISCV_ISA_EXT_SSTC:
case KVM_RISCV_ISA_EXT_SVINVAL:
+ case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
return false;
default:
break;
--
2.34.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v1] RISC-V: KVM: Allow Guest use Zihintpause extension
@ 2022-09-16 5:46 Mayuresh Chitale
2022-09-16 6:35 ` Conor.Dooley
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Mayuresh Chitale @ 2022-09-16 5:46 UTC (permalink / raw)
To: Anup Patel, Atish Patra; +Cc: Mayuresh Chitale, kvm-riscv, linux-riscv
We should advertise Zihintpause ISA extension to KVM user-space whenever
host supports it. This will allow KVM user-space (i.e. QEMU or KVMTOOL)
to pass on this information to Guest via ISA string.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index b6770ee08872..9085b90cf324 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_SVPBMT,
KVM_RISCV_ISA_EXT_SSTC,
KVM_RISCV_ISA_EXT_SVINVAL,
+ KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 901bb5c0cb50..0de0dd22e734 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
RISCV_ISA_EXT_SVPBMT,
RISCV_ISA_EXT_SSTC,
RISCV_ISA_EXT_SVINVAL,
+ RISCV_ISA_EXT_ZIHINTPAUSE,
};
static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_M:
case KVM_RISCV_ISA_EXT_SSTC:
case KVM_RISCV_ISA_EXT_SVINVAL:
+ case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
return false;
default:
break;
--
2.34.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v1] RISC-V: KVM: Allow Guest use Zihintpause extension
2022-09-16 5:46 Mayuresh Chitale
@ 2022-09-16 6:35 ` Conor.Dooley
2022-09-16 7:32 ` Andrew Jones
2022-09-20 18:28 ` Anup Patel
2 siblings, 0 replies; 5+ messages in thread
From: Conor.Dooley @ 2022-09-16 6:35 UTC (permalink / raw)
To: mchitale, anup, atishp; +Cc: kvm-riscv, linux-riscv
On 16/09/2022 06:46, Mayuresh Chitale wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> We should advertise Zihintpause ISA extension to KVM user-space whenever
> host supports it. This will allow KVM user-space (i.e. QEMU or KVMTOOL)
> to pass on this information to Guest via ISA string.
https://lore.kernel.org/linux-riscv/20220915152933.816459-1-mchitale@ventanamicro.com/
You sent a v1 yesterday, what changed between this "v1" & yesterday's
actual v1?
Thanks,
Conor.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index b6770ee08872..9085b90cf324 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_SVPBMT,
> KVM_RISCV_ISA_EXT_SSTC,
> KVM_RISCV_ISA_EXT_SVINVAL,
> + KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 901bb5c0cb50..0de0dd22e734 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> RISCV_ISA_EXT_SVPBMT,
> RISCV_ISA_EXT_SSTC,
> RISCV_ISA_EXT_SVINVAL,
> + RISCV_ISA_EXT_ZIHINTPAUSE,
> };
>
> static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
> @@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_M:
> case KVM_RISCV_ISA_EXT_SSTC:
> case KVM_RISCV_ISA_EXT_SVINVAL:
> + case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
> return false;
> default:
> break;
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1] RISC-V: KVM: Allow Guest use Zihintpause extension
2022-09-16 5:46 Mayuresh Chitale
2022-09-16 6:35 ` Conor.Dooley
@ 2022-09-16 7:32 ` Andrew Jones
2022-09-20 18:28 ` Anup Patel
2 siblings, 0 replies; 5+ messages in thread
From: Andrew Jones @ 2022-09-16 7:32 UTC (permalink / raw)
To: Mayuresh Chitale; +Cc: Anup Patel, Atish Patra, kvm-riscv, linux-riscv
On Fri, Sep 16, 2022 at 11:16:37AM +0530, Mayuresh Chitale wrote:
> We should advertise Zihintpause ISA extension to KVM user-space whenever
> host supports it. This will allow KVM user-space (i.e. QEMU or KVMTOOL)
> to pass on this information to Guest via ISA string.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> ---
Applies to riscv_kvm_queue.
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index b6770ee08872..9085b90cf324 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_SVPBMT,
> KVM_RISCV_ISA_EXT_SSTC,
> KVM_RISCV_ISA_EXT_SVINVAL,
> + KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 901bb5c0cb50..0de0dd22e734 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> RISCV_ISA_EXT_SVPBMT,
> RISCV_ISA_EXT_SSTC,
> RISCV_ISA_EXT_SVINVAL,
> + RISCV_ISA_EXT_ZIHINTPAUSE,
> };
>
> static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
> @@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_M:
> case KVM_RISCV_ISA_EXT_SSTC:
> case KVM_RISCV_ISA_EXT_SVINVAL:
> + case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
> return false;
> default:
> break;
> --
> 2.34.1
>
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1] RISC-V: KVM: Allow Guest use Zihintpause extension
2022-09-16 5:46 Mayuresh Chitale
2022-09-16 6:35 ` Conor.Dooley
2022-09-16 7:32 ` Andrew Jones
@ 2022-09-20 18:28 ` Anup Patel
2 siblings, 0 replies; 5+ messages in thread
From: Anup Patel @ 2022-09-20 18:28 UTC (permalink / raw)
To: Mayuresh Chitale; +Cc: Anup Patel, Atish Patra, kvm-riscv, linux-riscv
On Fri, Sep 16, 2022 at 11:17 AM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> We should advertise Zihintpause ISA extension to KVM user-space whenever
> host supports it. This will allow KVM user-space (i.e. QEMU or KVMTOOL)
> to pass on this information to Guest via ISA string.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
I have queued this patch for 6.1
Thanks,
Anup
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index b6770ee08872..9085b90cf324 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_SVPBMT,
> KVM_RISCV_ISA_EXT_SSTC,
> KVM_RISCV_ISA_EXT_SVINVAL,
> + KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 901bb5c0cb50..0de0dd22e734 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> RISCV_ISA_EXT_SVPBMT,
> RISCV_ISA_EXT_SSTC,
> RISCV_ISA_EXT_SVINVAL,
> + RISCV_ISA_EXT_ZIHINTPAUSE,
> };
>
> static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
> @@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_M:
> case KVM_RISCV_ISA_EXT_SSTC:
> case KVM_RISCV_ISA_EXT_SVINVAL:
> + case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
> return false;
> default:
> break;
> --
> 2.34.1
>
>
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv
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^ permalink raw reply [flat|nested] 5+ messages in thread
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