From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
linux-riscv@lists.infradead.org,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH] perf: RISC-V: fix failure for custom firmware events
Date: Mon, 19 Sep 2022 21:22:11 +0530 [thread overview]
Message-ID: <20220919155211.14453-1-mchitale@ventanamicro.com> (raw)
We can have SBI implementation specific firmware events in addition
to standard firmware events so we should not check firmware event code
against any limit. This patch removes the check so that programming
of the custom firmware events can be supported by the driver.
Fixes: e9991434596f5 ("RISC-V: Add perf platform driver based on SBI PMU extension")
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
drivers/perf/riscv_pmu_sbi.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 8de4ca2fef21..df044292615c 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -381,11 +381,8 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
bSoftware = config >> 63;
raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;
if (bSoftware) {
- if (raw_config_val < SBI_PMU_FW_MAX)
- ret = (raw_config_val & 0xFFFF) |
- (SBI_PMU_EVENT_TYPE_FW << 16);
- else
- return -EINVAL;
+ ret = (raw_config_val & 0xFFFF) |
+ (SBI_PMU_EVENT_TYPE_FW << 16);
} else {
ret = RISCV_PMU_RAW_EVENT_IDX;
*econfig = raw_config_val;
--
2.25.1
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next reply other threads:[~2022-09-19 15:57 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-19 15:52 Mayuresh Chitale [this message]
2022-09-20 8:30 ` [PATCH] perf: RISC-V: fix failure for custom firmware events Atish Patra
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