From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 8/8] riscv: remove riscv_isa_ext_keys[] array and related usage
Date: Thu, 6 Oct 2022 15:08:18 +0800 [thread overview]
Message-ID: <20221006070818.3616-9-jszhang@kernel.org> (raw)
In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org>
All users have switched to riscv_has_extension_*, removed unused
definitions, vars and related setting code.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/include/asm/hwcap.h | 28 ----------------------------
arch/riscv/kernel/cpufeature.c | 9 ---------
2 files changed, 37 deletions(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 54b88ee6cae1..f52fbc121ebe 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -62,18 +62,6 @@ enum {
extern unsigned long elf_hwcap;
-
-/*
- * This enum represents the logical ID for each RISC-V ISA extension static
- * keys. We can use static key to optimize code path if some ISA extensions
- * are available.
- */
-enum riscv_isa_ext_key {
- RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */
- RISCV_ISA_EXT_KEY_ZIHINTPAUSE,
- RISCV_ISA_EXT_KEY_MAX,
-};
-
struct riscv_isa_ext_data {
/* Name of the extension displayed to userspace via /proc/cpuinfo */
char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
@@ -81,22 +69,6 @@ struct riscv_isa_ext_data {
unsigned int isa_ext_id;
};
-extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
-
-static __always_inline int riscv_isa_ext2key(int num)
-{
- switch (num) {
- case RISCV_ISA_EXT_f:
- return RISCV_ISA_EXT_KEY_FPU;
- case RISCV_ISA_EXT_d:
- return RISCV_ISA_EXT_KEY_FPU;
- case RISCV_ISA_EXT_ZIHINTPAUSE:
- return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;
- default:
- return -EINVAL;
- }
-}
-
static __always_inline bool
riscv_has_extension_likely(const unsigned long ext)
{
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 2b1f18f97253..6bc3fb749274 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -28,9 +28,6 @@ unsigned long elf_hwcap __read_mostly;
/* Host ISA bitmap */
static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
-DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
-EXPORT_SYMBOL(riscv_isa_ext_keys);
-
/**
* riscv_isa_extension_base() - Get base extension word
*
@@ -242,12 +239,6 @@ void __init riscv_fill_hwcap(void)
if (elf_hwcap & BIT_MASK(i))
print_str[j++] = (char)('a' + i);
pr_info("riscv: ELF capabilities %s\n", print_str);
-
- for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) {
- j = riscv_isa_ext2key(i);
- if (j >= 0)
- static_branch_enable(&riscv_isa_ext_keys[j]);
- }
}
#ifdef CONFIG_RISCV_ALTERNATIVE
--
2.37.2
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next prev parent reply other threads:[~2022-10-06 7:18 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-06 7:08 [PATCH 0/8] riscv: improve boot time isa extensions handling Jisheng Zhang
2022-10-06 7:08 ` [PATCH 1/8] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2022-10-06 13:10 ` Andrew Jones
2022-10-06 17:44 ` Andrew Jones
2022-10-07 9:18 ` Heiko Stübner
2022-10-08 13:06 ` Conor Dooley
2022-10-08 13:59 ` Jisheng Zhang
2022-10-13 5:37 ` Conor Dooley
2022-10-06 7:08 ` [PATCH 2/8] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2022-10-06 13:12 ` Andrew Jones
2022-10-07 9:38 ` Heiko Stübner
2022-10-06 7:08 ` [PATCH 3/8] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2022-10-06 13:15 ` Andrew Jones
2022-10-07 9:22 ` Heiko Stübner
2022-10-06 7:08 ` [PATCH 4/8] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2022-10-06 13:31 ` Andrew Jones
2022-10-07 11:54 ` Heiko Stübner
2022-10-13 13:28 ` Heiko Stuebner
2022-10-06 7:08 ` [PATCH 5/8] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2022-10-06 13:36 ` Andrew Jones
2022-10-06 7:08 ` [PATCH 6/8] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2022-10-06 13:36 ` Andrew Jones
2022-10-07 15:11 ` Heiko Stübner
2022-10-06 7:08 ` [PATCH 7/8] riscv: cpu_relax: switch " Jisheng Zhang
2022-10-06 13:28 ` kernel test robot
2022-10-06 13:37 ` Andrew Jones
2022-10-07 15:12 ` Heiko Stübner
2022-10-07 18:14 ` kernel test robot
2022-10-06 7:08 ` Jisheng Zhang [this message]
2022-10-06 13:38 ` [PATCH 8/8] riscv: remove riscv_isa_ext_keys[] array and related usage Andrew Jones
2022-10-07 15:12 ` Heiko Stübner
2022-10-13 16:20 ` [PATCH 0/8] riscv: improve boot time isa extensions handling Andrew Jones
2022-10-29 9:56 ` Andrew Jones
2022-10-29 11:38 ` Jisheng Zhang
2022-10-30 16:03 ` Jisheng Zhang
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