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[31.30.173.61]) by smtp.gmail.com with ESMTPSA id z10-20020a50eb4a000000b0044e01e2533asm5901815edp.43.2022.10.06.06.37.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Oct 2022 06:37:29 -0700 (PDT) Date: Thu, 6 Oct 2022 15:37:28 +0200 From: Andrew Jones To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 7/8] riscv: cpu_relax: switch to riscv_has_extension_likely() Message-ID: <20221006133728.4ge3pmcm7mvksia7@kamzik> References: <20221006070818.3616-1-jszhang@kernel.org> <20221006070818.3616-8-jszhang@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221006070818.3616-8-jszhang@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221006_063731_231882_040D3CEB X-CRM114-Status: GOOD ( 15.67 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Oct 06, 2022 at 03:08:17PM +0800, Jisheng Zhang wrote: > Switch cpu_relax() from statich branch to the new helper > riscv_has_extension_likely() > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/vdso/processor.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h > index 1e4f8b4aef79..fb30480f36a0 100644 > --- a/arch/riscv/include/asm/vdso/processor.h > +++ b/arch/riscv/include/asm/vdso/processor.h > @@ -10,7 +10,7 @@ > > static inline void cpu_relax(void) > { > - if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) { > + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZIHINTPAUSE)) { > #ifdef __riscv_muldiv > int dummy; > /* In lieu of a halt instruction, induce a long-latency stall. */ > -- > 2.37.2 > Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv