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From: Heiko Stuebner <heiko@sntech.de>
To: atishp@atishpatra.org, anup@brainfault.org, will@kernel.org,
	mark.rutland@arm.com, paul.walmsley@sifive.com,
	palmer@dabbelt.com, aou@eecs.berkeley.edu
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Conor.Dooley@microchip.com, ajones@ventanamicro.com,
	Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v5 1/2] RISC-V: Cache SBI vendor values
Date: Mon, 10 Oct 2022 14:27:25 +0200	[thread overview]
Message-ID: <20221010122726.2405153-2-heiko@sntech.de> (raw)
In-Reply-To: <20221010122726.2405153-1-heiko@sntech.de>

sbi_get_mvendorid(), sbi_get_marchid() and sbi_get_mimpid() might get
called multiple times, though the values of these CSRs should not change
during the runtime of a specific machine.

So cache the values in the functions and prevent multiple ecalls
to read these values.

As Andrew Jones noted, at least marchid and mimpid may be negative
values when viewed as a long, so we use a separate static bool to
indiciate the cached status.

Suggested-by: Atish Patra <atishp@atishpatra.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/kernel/sbi.c | 30 +++++++++++++++++++++++++++---
 1 file changed, 27 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 775d3322b422..cc618aaa9d11 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -625,17 +625,41 @@ static inline long sbi_get_firmware_version(void)
 
 long sbi_get_mvendorid(void)
 {
-	return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
+	static long id;
+	static bool cached;
+
+	if (!cached) {
+		id = __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
+		cached = true;
+	}
+
+	return id;
 }
 
 long sbi_get_marchid(void)
 {
-	return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
+	static long id;
+	static bool cached;
+
+	if (!cached) {
+		id = __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
+		cached = true;
+	}
+
+	return id;
 }
 
 long sbi_get_mimpid(void)
 {
-	return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
+	static long id;
+	static bool cached;
+
+	if (!cached) {
+		id = __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
+		cached = true;
+	}
+
+	return id;
 }
 
 static void sbi_send_cpumask_ipi(const struct cpumask *target)
-- 
2.35.1


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  reply	other threads:[~2022-10-10 12:27 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-10 12:27 [PATCH v5 0/2] riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores Heiko Stuebner
2022-10-10 12:27 ` Heiko Stuebner [this message]
2022-10-10 12:45   ` [PATCH v5 1/2] RISC-V: Cache SBI vendor values Anup Patel
2022-10-10 12:54     ` Heiko Stuebner
2022-10-10 13:14       ` Anup Patel
2022-10-11  7:58         ` Heiko Stuebner
2022-10-10 12:27 ` [PATCH v5 2/2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores Heiko Stuebner

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