[PATCH AUTOSEL 6.0 20/67] clk: microchip: mpfs: add MSS pll's set & round rate

[PATCH AUTOSEL 6.0 20/67] clk: microchip: mpfs: add MSS pll's set & round rate

[Sasha Levin]

From: Conor Dooley <conor.dooley@microchip.com>

[ Upstream commit 14016e4aafc5f157c10fb1a386fa3b3bd9c30e9a ]

The MSS pll is not a fixed frequency clock, so add set() & round_rate()
support.
Control is limited to a 7 bit output divider as other devices on the
FPGA occupy the other three outputs of the PLL & prevent changing
the multiplier.

Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-9-conor.dooley@microchip.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/clk/microchip/clk-mpfs.c | 54 ++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c
index b6b89413e090..cb4ec4749279 100644
--- a/drivers/clk/microchip/clk-mpfs.c
+++ b/drivers/clk/microchip/clk-mpfs.c
@@ -126,8 +126,62 @@ static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned lon
 	return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv);
 }
 
+static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
+{
+	struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
+	void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
+	void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
+	u32 mult, ref_div;
+	unsigned long rate_before_ctrl;
+
+	mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
+	mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
+	ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
+	ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
+
+	rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
+
+	return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
+				  msspll_hw->flags);
+}
+
+static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
+{
+	struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
+	void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
+	void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
+	void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
+	u32 mult, ref_div, postdiv;
+	int divider_setting;
+	unsigned long rate_before_ctrl, flags;
+
+	mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
+	mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
+	ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
+	ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
+
+	rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
+	divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
+					  msspll_hw->flags);
+
+	if (divider_setting < 0)
+		return divider_setting;
+
+	spin_lock_irqsave(&mpfs_clk_lock, flags);
+
+	postdiv = readl_relaxed(postdiv_addr);
+	postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT);
+	writel_relaxed(postdiv, postdiv_addr);
+
+	spin_unlock_irqrestore(&mpfs_clk_lock, flags);
+
+	return 0;
+}
+
 static const struct clk_ops mpfs_clk_msspll_ops = {
 	.recalc_rate = mpfs_clk_msspll_recalc_rate,
+	.round_rate = mpfs_clk_msspll_round_rate,
+	.set_rate = mpfs_clk_msspll_set_rate,
 };
 
 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) {			\
-- 
2.35.1


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Re: [PATCH AUTOSEL 6.0 20/67] clk: microchip: mpfs: add MSS pll's set & round rate

[Conor Dooley]

Not a fix, NAK. Same for 5.19.

On 13 October 2022 01:15:01 IST, Sasha Levin <sashal@kernel.org> wrote:
>From: Conor Dooley <conor.dooley@microchip.com>
>
>[ Upstream commit 14016e4aafc5f157c10fb1a386fa3b3bd9c30e9a ]
>
>The MSS pll is not a fixed frequency clock, so add set() & round_rate()
>support.
>Control is limited to a 7 bit output divider as other devices on the
>FPGA occupy the other three outputs of the PLL & prevent changing
>the multiplier.
>
>Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
>Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>Link: https://lore.kernel.org/r/20220909123123.2699583-9-conor.dooley@microchip.com
>Signed-off-by: Sasha Levin <sashal@kernel.org>
>---
> drivers/clk/microchip/clk-mpfs.c | 54 ++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
>diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c
>index b6b89413e090..cb4ec4749279 100644
>--- a/drivers/clk/microchip/clk-mpfs.c
>+++ b/drivers/clk/microchip/clk-mpfs.c
>@@ -126,8 +126,62 @@ static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned lon
> 	return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv);
> }
> 
>+static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
>+{
>+	struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
>+	void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
>+	void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
>+	u32 mult, ref_div;
>+	unsigned long rate_before_ctrl;
>+
>+	mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
>+	mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
>+	ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
>+	ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
>+
>+	rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
>+
>+	return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
>+				  msspll_hw->flags);
>+}
>+
>+static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
>+{
>+	struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
>+	void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
>+	void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
>+	void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
>+	u32 mult, ref_div, postdiv;
>+	int divider_setting;
>+	unsigned long rate_before_ctrl, flags;
>+
>+	mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
>+	mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
>+	ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
>+	ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
>+
>+	rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
>+	divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
>+					  msspll_hw->flags);
>+
>+	if (divider_setting < 0)
>+		return divider_setting;
>+
>+	spin_lock_irqsave(&mpfs_clk_lock, flags);
>+
>+	postdiv = readl_relaxed(postdiv_addr);
>+	postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT);
>+	writel_relaxed(postdiv, postdiv_addr);
>+
>+	spin_unlock_irqrestore(&mpfs_clk_lock, flags);
>+
>+	return 0;
>+}
>+
> static const struct clk_ops mpfs_clk_msspll_ops = {
> 	.recalc_rate = mpfs_clk_msspll_recalc_rate,
>+	.round_rate = mpfs_clk_msspll_round_rate,
>+	.set_rate = mpfs_clk_msspll_set_rate,
> };
> 
> #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) {			\

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Re: [PATCH AUTOSEL 6.0 20/67] clk: microchip: mpfs: add MSS pll's set & round rate

[Sasha Levin]

On Thu, Oct 13, 2022 at 06:29:03AM +0100, Conor Dooley wrote:
>Not a fix, NAK. Same for 5.19.

Ack

-- 
Thanks,
Sasha

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