Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree

Conor Dooley
2022-11-20T11:02:53Z

On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote:
> Add a baisc dtsi for the bouffalolab bl808 SoC.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
> 2 files changed, 75 insertions(+)
> create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b525467152b2 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> +subdir-y += bouffalolab
> subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> new file mode 100644
> index 000000000000..c98ebb14ee10
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "bouffalolab,bl808";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + timebase-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";

So this is not yet defined as the dt etc for the d1 has not yet landed.
I think I will go pick up that patch for v6.2 as it should make
everyone's life easier.

Without that, dtbs_check produces:
arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtb:0:0: /cpus/cpu@0: failed to match any schema with compatible: ['thead,c906', 'riscv']

> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <256>;
> + d-cache-size = <32768>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + xtal: xtal-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <40000000>;
> + clock-output-names = "xtal";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + ranges;
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + uart0: serial@30002000 {
> + compatible = "bouffalolab,uart";
> + reg = <0x30002000 0x1000>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&xtal>;
> + status = "disabled";
> + };
> +
> + plic: interrupt-controller@e0000000 {
> + compatible = "thead,c900-plic";

Hmm, this one fails validation too. Likely you need to add a
"bouffalolab,plic" to the plic dt-binding or otherwise modify the
binding such that thead,c900-plic on it's own is permitted. CC Samuel on
that patch please in case he has an opinion on it.

Also, I've taken over picking up the misc dt stuff that Palmer used to
apply - so canaan, starfive & sifive stuff. Do you intended sending PRs
to Arnd for this stuff, or would you like to me bundle it with what I am
going to be sending anyway?

Thanks,
Conor.

> + reg = <0xe0000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 0xffffffff>,
> + <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <64>;
> + };
> + };
> +};
> --
> 2.37.2