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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id u9-20020a1709061da900b0074136cac2e7sm1716343ejh.81.2022.11.21.02.53.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Nov 2022 02:53:34 -0800 (PST) Date: Mon, 21 Nov 2022 11:53:33 +0100 From: Andrew Jones To: Chen Lifu Cc: anup@brainfault.org, atishp@atishpatra.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH -next] RISC-V: KVM: optimize kvm_arch_hardware_enable() Message-ID: <20221121105333.rap67cpmst3odiid@kamzik> References: <20221121003915.2817102-1-chenlifu@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221121003915.2817102-1-chenlifu@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221121_025340_723574_9D5D2337 X-CRM114-Status: GOOD ( 18.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Nov 21, 2022 at 08:39:15AM +0800, Chen Lifu wrote: > The values of CSR_HEDELEG and CSR_HIDELEG registers are constants, > so change them from variables to macros. > > Signed-off-by: Chen Lifu > --- > arch/riscv/kvm/main.c | 31 +++++++++++++------------------ > 1 file changed, 13 insertions(+), 18 deletions(-) > > diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c > index df2d8716851f..70196b03b6f9 100644 > --- a/arch/riscv/kvm/main.c > +++ b/arch/riscv/kvm/main.c > @@ -12,10 +12,21 @@ > #include > #include > #include > #include > > +#define EXC_HEDELEG ((1UL << EXC_INST_MISALIGNED) | \ > + (1UL << EXC_BREAKPOINT) | \ > + (1UL << EXC_SYSCALL) | \ > + (1UL << EXC_INST_PAGE_FAULT) | \ > + (1UL << EXC_LOAD_PAGE_FAULT) | \ > + (1UL << EXC_STORE_PAGE_FAULT)) > + > +#define IRQ_HIDELEG ((1UL << IRQ_VS_SOFT) | \ > + (1UL << IRQ_VS_TIMER) | \ > + (1UL << IRQ_VS_EXT)) > + > long kvm_arch_dev_ioctl(struct file *filp, > unsigned int ioctl, unsigned long arg) > { > return -EINVAL; > } > @@ -30,29 +41,13 @@ int kvm_arch_hardware_setup(void *opaque) > return 0; > } > > int kvm_arch_hardware_enable(void) > { > - unsigned long hideleg, hedeleg; > - > - hedeleg = 0; > - hedeleg |= (1UL << EXC_INST_MISALIGNED); > - hedeleg |= (1UL << EXC_BREAKPOINT); > - hedeleg |= (1UL << EXC_SYSCALL); > - hedeleg |= (1UL << EXC_INST_PAGE_FAULT); > - hedeleg |= (1UL << EXC_LOAD_PAGE_FAULT); > - hedeleg |= (1UL << EXC_STORE_PAGE_FAULT); > - csr_write(CSR_HEDELEG, hedeleg); > - > - hideleg = 0; > - hideleg |= (1UL << IRQ_VS_SOFT); > - hideleg |= (1UL << IRQ_VS_TIMER); > - hideleg |= (1UL << IRQ_VS_EXT); > - csr_write(CSR_HIDELEG, hideleg); > - > + csr_write(CSR_HEDELEG, EXC_HEDELEG); > + csr_write(CSR_HIDELEG, IRQ_HIDELEG); > csr_write(CSR_HCOUNTEREN, -1UL); > - > csr_write(CSR_HVIP, 0); > > return 0; > } > > -- > 2.37.1 > I don't think this optimizes anything. I'm pretty sure the compiler will load the input to csr_write() in the most efficient way it can, regardless of using a constant or building the input out of constants. This could maybe be considered a code cleanup, but, in this case, it's really in the eye of the beholder. Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv