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From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Christoph Hellwig <hch@infradead.org>,
	Damien Le Moal <damien.lemoal@opensource.wdc.com>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Samuel Holland <samuel@sholland.org>
Subject: [PATCH v1 3/7] RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO
Date: Mon, 21 Nov 2022 22:14:11 +0000	[thread overview]
Message-ID: <20221121221414.109965-4-conor@kernel.org> (raw)
In-Reply-To: <20221121221414.109965-1-conor@kernel.org>

From: Conor Dooley <conor.dooley@microchip.com>

Convert all non user visible use of SOC_FOO symbols to their ARCH_FOO
variants. The canaan DTs are an outlier in that they're gated at the
directory and the file level. Drop the directory level gating while we
are swapping the symbol names over.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/Makefile                    |  2 +-
 arch/riscv/boot/dts/Makefile           |  2 +-
 arch/riscv/boot/dts/canaan/Makefile    | 14 +++++++-------
 arch/riscv/boot/dts/microchip/Makefile |  8 ++++----
 arch/riscv/boot/dts/sifive/Makefile    |  4 ++--
 arch/riscv/boot/dts/starfive/Makefile  |  2 +-
 6 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 0d13b597cb55..46a520c1273c 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -131,7 +131,7 @@ endif
 endif
 
 ifneq ($(CONFIG_XIP_KERNEL),y)
-ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN),yy)
+ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy)
 KBUILD_IMAGE := $(boot)/loader.bin
 else
 ifeq ($(CONFIG_EFI_ZBOOT),)
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index b0ff5fbabb0c..0c97d673b775 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += sifive
 subdir-y += starfive
-subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
+subdir-y += canaan
 subdir-y += microchip
 subdir-y += renesas
 
diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile
index befe4eb7527b..520623264c87 100644
--- a/arch/riscv/boot/dts/canaan/Makefile
+++ b/arch/riscv/boot/dts/canaan/Makefile
@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_CANAAN) += canaan_kd233.dtb
-dtb-$(CONFIG_SOC_CANAAN) += k210_generic.dtb
-dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_bit.dtb
-dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_dock.dtb
-dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_go.dtb
-dtb-$(CONFIG_SOC_CANAAN) += sipeed_maixduino.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maixduino.dtb
 
-obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))
+obj-$(CONFIG_ARCH_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_ARCH_CANAAN_K210_DTB_SOURCE))
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 7427a20934f3..259c3c802cab 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
-dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
-dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
-dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
index d90e4eb0ade8..6a5fbd4ed96a 100644
--- a/arch/riscv/boot/dts/sifive/Makefile
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
-			    hifive-unmatched-a00.dtb
+dtb-$(CONFIG_ARCH_SIFIVE) += hifive-unleashed-a00.dtb \
+			     hifive-unmatched-a00.dtb
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 039c143cba33..7b00a48580ca 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,2 +1,2 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
-- 
2.37.2


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  parent reply	other threads:[~2022-11-21 22:18 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-21 22:14 [PATCH v1 0/7] RISC-V: kconfig.socs cleanup, part 1 Conor Dooley
2022-11-21 22:14 ` [PATCH v1 1/7] RISC-V: introduce ARCH_FOO kconfig aliases for SOC_FOO symbols Conor Dooley
2023-01-10 21:14   ` Geert Uytterhoeven
2023-01-10 21:39     ` Conor Dooley
2023-01-11  7:46       ` Geert Uytterhoeven
2023-01-10 22:22     ` Damien Le Moal
2023-01-10 22:34       ` Conor Dooley
2023-01-10 22:47         ` Damien Le Moal
2023-01-11  7:50           ` Geert Uytterhoeven
2022-11-21 22:14 ` [PATCH v1 2/7] RISC-V: kconfig.socs: convert usage of SOC_CANAAN to ARCH_CANAAN Conor Dooley
2022-11-21 22:14 ` Conor Dooley [this message]
2022-11-22  6:04   ` [PATCH v1 3/7] RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO Christoph Hellwig
2022-12-09  1:24     ` Palmer Dabbelt
2022-11-21 22:14 ` [PATCH v1 4/7] RISC-V: stop selecting SIFIVE_PLIC at the SoC level Conor Dooley
2022-11-21 22:14 ` [PATCH v1 5/7] RISC-V: stop selecting the PolarFire SoC clock driver Conor Dooley
2022-11-22  8:35   ` Geert Uytterhoeven
2022-11-22  8:40     ` Conor.Dooley
2022-11-21 22:14 ` [PATCH v1 6/7] RISC-V: stop selecting SiFive clock and serial drivers directly Conor Dooley
2022-11-21 22:14 ` [PATCH v1 7/7] RISC-V: stop directly selecting drivers for SOC_CANAAN Conor Dooley

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