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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Nov 24, 2022 at 12:26:12AM -0800, Deepak Gupta wrote: >On Thu, Nov 24, 2022 at 09:32:19AM +0800, Guo Ren wrote: >>>+.macro asm_per_cpu dst sym tmp >>>+ REG_L \tmp, TASK_TI_CPU_NUM(tp) >>>+ slli \tmp, \tmp, 0x3 >>>+ la \dst, __per_cpu_offset >>>+ add \dst, \dst, \tmp >>>+ REG_L \tmp, 0(\dst) >>>+ la \dst, \sym >>>+ add \dst, \dst, \tmp >>Another tricky asm code of using percpu, I don't know how the percpu >>maintenance guy thinks. > >On this, if you can point me to someone, I would like to get their feedback. >While discussing this, one issue that comes in my mind is if the shift >of 0x3 is correct or not on 32bit systems. I don't know what's the >size of each entry >in `__per_cpu_offset`. On 64bit it's 8 bytes and thus 3 bit shift. Yes this would need a fix for 32bit. `__per_cpu_offset` is an array of `unsigned long` and thus shift should be 2 bit on 32bit systems. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv