[PATCH v1 1/3] dt-bindings: watchdog: Add watchdog for StarFive

[xingu.wu <xingyu.wu@starfivetech.com>]

From: Xingyu Wu <xingyu.wu@starfivetech.com>

Add bindings to describe the watchdog for the StarFive SoCs.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 .../bindings/watchdog/starfive,wdt.yaml       | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/watchdog/starfive,wdt.yaml

diff --git a/Documentation/devicetree/bindings/watchdog/starfive,wdt.yaml b/Documentation/devicetree/bindings/watchdog/starfive,wdt.yaml
new file mode 100644
index 000000000000..ece3e80153a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/starfive,wdt.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/starfive,wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive Watchdog
+
+allOf:
+  - $ref: "watchdog.yaml#"
+
+maintainers:
+  - Samin Guo <samin.guo@starfivetech.com>
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+properties:
+  compatible:
+    const: starfive,jh7110-wdt
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Core clock
+      - description: APB clock
+
+  clock-names:
+    items:
+      - const: core_clk
+      - const: apb_clk
+
+  resets:
+    items:
+      - description: APB reset
+      - description: Core reset
+
+  reset-names:
+    items:
+      - const: rst_apb
+      - const: rst_core
+
+  timeout-sec: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - timeout-sec
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110.h>
+    #include <dt-bindings/reset/starfive-jh7110.h>
+
+    watchdog@13070000 {
+            compatible = "starfive,jh7110-wdt";
+            reg = <0x13070000 0x10000>;
+            interrupts = <68>;
+            clocks = <&syscrg_clk JH7110_SYSCLK_WDT_CORE>,
+                     <&syscrg_clk JH7110_SYSCLK_WDT_APB>;
+            clock-names = "core_clk", "apb_clk";
+            resets = <&syscrg_rst JH7110_SYSRST_WDT_APB>,
+                     <&syscrg_rst JH7110_SYSRST_WDT_CORE>;
+            reset-names = "rst_apb", "rst_core";
+            timeout-sec = <15>;
+    };
+
-- 
2.25.1


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