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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id bg42-20020a05600c3caa00b003b4cba4ef71sm21447657wmb.41.2023.01.10.00.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 00:44:26 -0800 (PST) Date: Tue, 10 Jan 2023 09:44:25 +0100 From: Andrew Jones To: Heiko Stuebner Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com, christoph.muellner@vrull.eu, conor@kernel.org, philipp.tomsich@vrull.eu, jszhang@kernel.org, Heiko Stuebner Subject: Re: [PATCH v4 2/5] RISC-V: add helpers for J-type immediate handling Message-ID: <20230110084425.wupytnd5juzowzme@orel> References: <20230109181755.2383085-1-heiko@sntech.de> <20230109181755.2383085-3-heiko@sntech.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230109181755.2383085-3-heiko@sntech.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230110_004432_922804_4ACF369B X-CRM114-Status: GOOD ( 22.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jan 09, 2023 at 07:17:52PM +0100, Heiko Stuebner wrote: > From: Heiko Stuebner > > Similar to the helper for the u-type + i-type imm handling, add helper- > functions for j-type immediates. > > While it also would be possible to open-code that bit of imm wiggling > using the macros already provided in insn.h, it's way better to have > consistency on how we handle this across all function encoding/decoding. > > Signed-off-by: Heiko Stuebner > --- > arch/riscv/include/asm/insn.h | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h > index 0455b4dcb0a7..9eea61a3028f 100644 > --- a/arch/riscv/include/asm/insn.h > +++ b/arch/riscv/include/asm/insn.h > @@ -301,6 +301,32 @@ static __always_inline bool riscv_insn_is_branch(u32 code) > (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \ > (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); }) > > +/* > + * Get the immediate from a J-type instruction. > + * > + * @insn: instruction to process > + * Return: immediate > + */ > +static inline s32 riscv_insn_extract_jtype_imm(u32 insn) > +{ > + return RV_EXTRACT_JTYPE_IMM(insn); > +} > + > +/* > + * Update a J-type instruction with an immediate value. > + * > + * @insn: pointer to the jtype instruction > + * @imm: the immediate to insert into the instruction > + */ > +static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm) > +{ > + *insn &= ~GENMASK(31, 12); > + *insn |= (((imm & (RV_J_IMM_10_1_MASK << RV_J_IMM_10_1_OFF)) << RV_I_IMM_11_0_OPOFF) | ^ RV_J_IMM_10_1_OPOFF (as pointed out by Conor) > + ((imm & (RV_J_IMM_11_MASK << RV_J_IMM_11_OFF)) << RV_J_IMM_11_OPOFF) | > + ((imm & (RV_J_IMM_19_12_OPOFF << RV_J_IMM_19_12_OFF)) << RV_J_IMM_19_12_OPOFF) | ^ RV_J_IMM_19_12_MASK > + ((imm & (1 << RV_J_IMM_SIGN_OFF)) << RV_J_IMM_SIGN_OPOFF)); nit: can drop the outermost () > +} > + > /* > * Put together one immediate from a U-type and I-type instruction pair. > * > -- > 2.35.1 > Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv