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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id r16-20020a0568080ab000b0035bce2a39c7sm8351022oij.21.2023.01.12.12.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 12:49:14 -0800 (PST) Received: (nullmailer pid 214366 invoked by uid 1000); Thu, 12 Jan 2023 20:49:13 -0000 Date: Thu, 12 Jan 2023 14:49:13 -0600 From: Rob Herring To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Krzysztof Kozlowski , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 4/9] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Message-ID: <20230112204913.GA126944-robh@kernel.org> References: <20230103141409.772298-1-apatel@ventanamicro.com> <20230103141409.772298-5-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230103141409.772298-5-apatel@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230112_124917_510660_E1FA0B05 X-CRM114-Status: GOOD ( 29.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Jan 03, 2023 at 07:44:04PM +0530, Anup Patel wrote: > We add DT bindings document for the RISC-V incoming MSI controller > (IMSIC) defined by the RISC-V advanced interrupt architecture (AIA) > specification. > > Signed-off-by: Anup Patel > --- > .../interrupt-controller/riscv,imsics.yaml | 168 ++++++++++++++++++ > 1 file changed, 168 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml > new file mode 100644 > index 000000000000..b9db03b6e95f > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml > @@ -0,0 +1,168 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V Incoming MSI Controller (IMSIC) > + > +maintainers: > + - Anup Patel > + > +description: | > + The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming > + MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V > + AIA specification can be found at https://github.com/riscv/riscv-aia. > + > + The IMSIC is a per-CPU (or per-HART) device with separate interrupt file > + for each privilege level (machine or supervisor). The configuration of > + a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO > + space to receive MSIs from devices. Each IMSIC interrupt file supports a > + fixed number of interrupt identities (to distinguish MSIs from devices) > + which is same for given privilege level across CPUs (or HARTs). > + > + The device tree of a RISC-V platform will have one IMSIC device tree node > + for each privilege level (machine or supervisor) which collectively describe > + IMSIC interrupt files at that privilege level across CPUs (or HARTs). > + > + The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform > + follows a particular scheme defined by the RISC-V AIA specification. A IMSIC > + group is a set of IMSIC interrupt files co-located in MMIO space and we can > + have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a > + RISC-V platform. The MSI target address of a IMSIC interrupt file at given > + privilege level (machine or supervisor) encodes group index, HART index, > + and guest index (shown below). > + > + XLEN-1 >=24 12 0 > + | | | | > + ------------------------------------------------------------- > + |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | > + ------------------------------------------------------------- > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - riscv,qemu-imsics The implmentation/vendor is qemu, so: qemu,imsics (or qemu,riscv-imsics?) > + - const: riscv,imsics > + > + reg: > + minItems: 1 > + maxItems: 16384 > + description: > + Base address of each IMSIC group. > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 0 > + > + msi-controller: true > + > + interrupts-extended: > + minItems: 1 > + maxItems: 16384 > + description: > + This property represents the set of CPUs (or HARTs) for which given > + device tree node describes the IMSIC interrupt files. Each node pointed > + to should be a riscv,cpu-intc node, which has a riscv node (i.e. RISC-V > + HART) as parent. > + > + riscv,num-ids: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 63 > + maximum: 2047 > + description: > + Number of interrupt identities supported by IMSIC interrupt file. > + > + riscv,num-guest-ids: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 63 > + maximum: 2047 > + description: > + Number of interrupt identities are supported by IMSIC guest interrupt > + file. When not specified it is assumed to be same as specified by the > + riscv,num-ids property. > + > + riscv,guest-index-bits: > + minimum: 0 > + maximum: 7 > + default: 0 > + description: > + Number of guest index bits in the MSI target address. When not > + specified it is assumed to be 0. No need to repeat what 'default: 0' defines. > + > + riscv,hart-index-bits: > + minimum: 0 > + maximum: 15 > + description: > + Number of HART index bits in the MSI target address. When not > + specified it is estimated based on the interrupts-extended property. If guessing works, why do you need the property? Perhaps s/estimated/calculated/? > + > + riscv,group-index-bits: > + minimum: 0 > + maximum: 7 > + default: 0 > + description: > + Number of group index bits in the MSI target address. When not > + specified it is assumed to be 0. > + > + riscv,group-index-shift: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 55 > + default: 24 > + description: > + The least significant bit position of the group index bits in the > + MSI target address. When not specified it is assumed to be 24. > + > +required: > + - compatible > + - reg > + - interrupt-controller > + - msi-controller #msi-cells should be defined (as 0) and required. Best to be explicit #and not rely on the default. > + - interrupts-extended > + - riscv,num-ids > + > +unevaluatedProperties: false > + > +examples: > + - | > + // Example 1 (Machine-level IMSIC files with just one group): > + > + imsic_mlevel: interrupt-controller@24000000 { Drop unused labels. > + compatible = "riscv,qemu-imsics", "riscv,imsics"; > + interrupts-extended = <&cpu1_intc 11>, > + <&cpu2_intc 11>, > + <&cpu3_intc 11>, > + <&cpu4_intc 11>; > + reg = <0x28000000 0x4000>; > + interrupt-controller; > + #interrupt-cells = <0>; > + msi-controller; > + riscv,num-ids = <127>; > + }; > + > + - | > + // Example 2 (Supervisor-level IMSIC files with two groups): > + > + imsic_slevel: interrupt-controller@28000000 { > + compatible = "riscv,qemu-imsics", "riscv,imsics"; > + interrupts-extended = <&cpu1_intc 9>, > + <&cpu2_intc 9>, > + <&cpu3_intc 9>, > + <&cpu4_intc 9>; > + reg = <0x28000000 0x2000>, /* Group0 IMSICs */ > + <0x29000000 0x2000>; /* Group1 IMSICs */ > + interrupt-controller; > + #interrupt-cells = <0>; > + msi-controller; > + riscv,num-ids = <127>; > + riscv,group-index-bits = <1>; > + riscv,group-index-shift = <24>; > + }; > +... > -- > 2.34.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv