Re: [PATCH v4 1/4] dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl

Hal Feng
2023-02-06T16:31:47Z

On Mon, 6 Feb 2023 10:10:16 -0600, Rob Herring wrote:
> On Fri, Feb 03, 2023 at 10:17:58PM +0800, Hal Feng wrote:
>> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
>> new file mode 100644
>> index 000000000000..22554e68ec91
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
>> @@ -0,0 +1,141 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SYS Pin Controller
>> +
>> +description: |
>> + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
>> +
>> + Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63
>> + can be multiplexed and have configurable bias, drive strength,
>> + schmitt trigger etc.
>> + Some peripherals have their I/O go through the 64 "GPIOs". This also
>> + includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
>> + All these peripherals are connected to all 64 GPIOs such that
>> + any GPIO can be set up to be controlled by any of the peripherals.
>> +
>> +maintainers:
>> + - Jianlong Huang <jianlong.huang@starfivetech.com>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-sys-pinctrl
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + resets:
>> + maxItems: 1
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + interrupt-controller: true
>> +
>> + '#interrupt-cells':
>> + const: 2
>> +
>> + gpio-controller: true
>> +
>> + '#gpio-cells':
>> + const: 2
>> +
>> +patternProperties:
>> + '-[0-9]+$':
>> + type: object
>> + additionalProperties: false
>> + patternProperties:
>> + '-pins$':
>> + type: object
>> + description: |
>> + A pinctrl node should contain at least one subnode representing the
>> + pinctrl groups available on the machine. Each subnode will list the
>> + pins it needs, and how they should be configured, with regard to
>> + muxer configuration, bias, input enable/disable, input schmitt
>> + trigger enable/disable, slew-rate and drive strength.
>> + $ref: /schemas/pinctrl/pincfg-node.yaml
>
> On 2nd look, this should be:
>
> allOf:
> - $ref: /schemas/pinctrl/pincfg-node.yaml
> - $ref: /schemas/pinctrl/pinmux-node.yaml

Will fix accordingly. Thanks.

>
>> + additionalProperties: false
>> +
>> + properties:
>> + pinmux:
>> + description: |
>> + The list of GPIOs and their mux settings that properties in the
>> + node apply to. This should be set using the GPIOMUX or PINMUX
>> + macros.
>> + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux
>
> And drop this.
>
> Same in other patch. With that, Reviewed-by stands.

Will fix it. Thank you for your review.

Best regards,
Hal