Re: [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA

Vinod Koul
2023-02-10T08:59:41Z

On 06-02-23, 19:38, Walker Chen wrote:
> Adding DMA reset operation in device probe, and using different
> registers according to the hardware handshake number.

subsystem tag is dmaengine: xxx

>
> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
> ---
> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++---
> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++
> 2 files changed, 24 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index a183d93bd7e2..3581810033d2 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -25,6 +25,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/types.h>
>
> @@ -86,7 +87,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>
> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
> - if (chan->chip->dw->hdata->reg_map_8_channels) {
> + if (chan->chip->dw->hdata->reg_map_8_channels &&
> + !chan->chip->dw->hdata->use_cfg2) {

what about older/other platforms that dont have use_cfg2?

> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
> @@ -541,8 +543,6 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
> (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
> reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
> lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
> -
> - return;
> }
>
> /*
> @@ -1136,7 +1136,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
> axi_chan_disable(chan);
>
> ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
> - !(val & chan_active), 1000, 10000);
> + !(val & chan_active), 1000, DMAC_TIMEOUT_US);
> if (ret == -ETIMEDOUT)
> dev_warn(dchan2dev(dchan),
> "%s failed to stop\n", axi_chan_name(chan));
> @@ -1323,6 +1323,12 @@ static int parse_device_properties(struct axi_dma_chip *chip)
>
> chip->dw->hdata->m_data_width = tmp;
>
> + ret = device_property_read_u32(dev, "snps,num-hs-if", &tmp);
> + if (!ret) {
> + if (tmp > 16)
> + chip->dw->hdata->use_cfg2 = true;
> + }
> +
> ret = device_property_read_u32_array(dev, "snps,block-size", carr,
> chip->dw->hdata->nr_channels);
> if (ret)
> @@ -1410,6 +1416,16 @@ static int dw_probe(struct platform_device *pdev)
> if (IS_ERR(chip->cfgr_clk))
> return PTR_ERR(chip->cfgr_clk);
>
> + if (of_device_is_compatible(node, "starfive,axi-dma")) {
> + chip->resets = devm_reset_control_array_get_exclusive(&pdev->dev);
> + if (IS_ERR(chip->resets))
> + return PTR_ERR(chip->resets);
> +
> + ret = reset_control_deassert(chip->resets);
> + if (ret)
> + return ret;
> + }
> +
> ret = parse_device_properties(chip);
> if (ret)
> return ret;
> @@ -1554,6 +1570,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
> static const struct of_device_id dw_dma_of_id_table[] = {
> { .compatible = "snps,axi-dma-1.01a" },
> { .compatible = "intel,kmb-axi-dma" },
> + { .compatible = "starfive,axi-dma" },
> {}
> };
> MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index e9d5eb0fd594..761d95691c02 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -21,6 +21,7 @@
> #define DMAC_MAX_CHANNELS 16
> #define DMAC_MAX_MASTERS 2
> #define DMAC_MAX_BLK_SIZE 0x200000
> +#define DMAC_TIMEOUT_US 200000
>
> struct dw_axi_dma_hcfg {
> u32 nr_channels;
> @@ -33,6 +34,7 @@ struct dw_axi_dma_hcfg {
> /* Register map for DMAX_NUM_CHANNELS <= 8 */
> bool reg_map_8_channels;
> bool restrict_axi_burst_len;
> + bool use_cfg2;
> };
>
> struct axi_dma_chan {
> @@ -70,6 +72,7 @@ struct axi_dma_chip {
> struct clk *core_clk;
> struct clk *cfgr_clk;
> struct dw_axi_dma *dw;
> + struct reset_control *resets;
> };
>
> /* LLI == Linked List Item */
> --
> 2.17.1

--
~Vinod