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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id q2-20020a0568080ec200b0037d6c3fc8aasm616760oiv.45.2023.02.10.10.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 10:29:36 -0800 (PST) Received: (nullmailer pid 2916782 invoked by uid 1000); Fri, 10 Feb 2023 18:29:35 -0000 Date: Fri, 10 Feb 2023 12:29:35 -0600 From: Rob Herring To: Changhuang Liang Cc: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Jack Zhu , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v1 2/4] dt-bindings: phy: Add starfive,jh7110-dphy-rx Message-ID: <20230210182935.GA2914589-robh@kernel.org> References: <20230210061713.6449-1-changhuang.liang@starfivetech.com> <20230210061713.6449-3-changhuang.liang@starfivetech.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230210061713.6449-3-changhuang.liang@starfivetech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230210_102943_571937_0EAA4223 X-CRM114-Status: GOOD ( 19.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Feb 09, 2023 at 10:17:11PM -0800, Changhuang Liang wrote: > Starfive SoC like the jh7110 use a MIPI D-PHY RX controller based on > a M31 IP. Add a binding for it. > > Signed-off-by: Changhuang Liang > --- > .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 78 +++++++++++++++++++ > 1 file changed, 78 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > > diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > new file mode 100644 > index 000000000000..1c1e5c7cbee2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > @@ -0,0 +1,78 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Starfive SoC MIPI D-PHY Rx Controller > + > +maintainers: > + - Jack Zhu > + - Changhuang Liang > + > +description: | Don't need '|' > + The Starfive SOC has a MIPI CSI D-PHY based on M31 IP use to transfer > + the CSI cameras data. > + > +properties: > + compatible: > + items: > + - const: "starfive,jh7110-dphy-rx" Drop quotes. > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 3 > + maxItems: 3 Just maxItems is enough. > + > + clock-names: > + items: > + - const: cfg > + - const: ref > + - const: tx > + > + resets: > + minItems: 2 > + maxItems: 2 Need to define what each reset is. > + > + starfive,aon-syscon: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' Drop quotes. > + items: > + items: > + - description: phandle of AON SYSCON > + - description: register offset > + description: The register of dphy rx driver can be configured > + by AON SYSCON in this property. > + > + "#phy-cells": > + const: 0 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - starfive,aon-syscon > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + dphy@19820000 { > + compatible = "starfive,jh7110-dphy-rx"; > + reg = <0x19820000 0x10000>; > + clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFGCLK_IN>, > + <&ispcrg JH7110_ISPCLK_M31DPHY_REFCLK_IN>, > + <&ispcrg JH7110_ISPCLK_M31DPHY_TXCLKESC_LAN0>; > + clock-names = "cfg", "ref", "tx"; > + resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>, > + <&ispcrg JH7110_ISPRST_M31DPHY_B09_ALWAYS_ON>; > + starfive,aon-syscon = <&aon_syscon 0x00>; > + #phy-cells = <0>; > + }; > -- > 2.25.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv