From: Andrew Jones <ajones@ventanamicro.com>
To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
kvm-riscv@lists.infradead.org
Cc: 'Rob Herring ' <robh@kernel.org>,
'Jisheng Zhang ' <jszhang@kernel.org>,
'Anup Patel ' <apatel@ventanamicro.com>,
'Conor Dooley ' <conor.dooley@microchip.com>,
'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org>,
'Heiko Stuebner ' <heiko@sntech.de>,
'Paul Walmsley ' <paul.walmsley@sifive.com>,
'Palmer Dabbelt ' <palmer@dabbelt.com>,
'Albert Ou ' <aou@eecs.berkeley.edu>,
'Ben Dooks ' <ben.dooks@codethink.co.uk>,
'Atish Patra ' <atishp@rivosinc.com>
Subject: [PATCH v5 3/8] dt-bindings: riscv: Document cboz-block-size
Date: Tue, 21 Feb 2023 20:09:11 +0100 [thread overview]
Message-ID: <20230221190916.572454-4-ajones@ventanamicro.com> (raw)
In-Reply-To: <20230221190916.572454-1-ajones@ventanamicro.com>
The Zicboz operation (cbo.zero) operates on a block-size defined
for the cpu-core. While we already have the riscv,cbom-block-size
property, it only provides the block size for Zicbom operations.
Even though it's likely Zicboz and Zicbom will use the same size,
that's not required by the specification. Create another property
specifically for Zicboz.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 001931d526ec..f24cf9601c6e 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -72,6 +72,11 @@ properties:
description:
The blocksize in bytes for the Zicbom cache operations.
+ riscv,cboz-block-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The blocksize in bytes for the Zicboz cache operations.
+
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture
--
2.39.1
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next prev parent reply other threads:[~2023-02-21 20:15 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 19:09 [PATCH v5 0/8] RISC-V: Apply Zicboz to clear_page Andrew Jones
2023-02-21 19:09 ` [PATCH v5 1/8] RISC-V: alternatives: Support patching multiple insns in assembly Andrew Jones
2023-02-21 19:09 ` [PATCH v5 2/8] RISC-V: Factor out body of riscv_init_cbom_blocksize loop Andrew Jones
2023-02-21 19:09 ` Andrew Jones [this message]
2023-02-21 19:09 ` [PATCH v5 4/8] RISC-V: Add Zicboz detection and block size parsing Andrew Jones
2023-02-21 19:09 ` [PATCH v5 5/8] riscv: cpufeatures: Put the upper 16 bits of patch ID to work Andrew Jones
2023-02-22 17:27 ` Conor Dooley
2023-02-23 12:53 ` Andrew Jones
2023-02-21 19:09 ` [PATCH v5 6/8] RISC-V: Use Zicboz in clear_page when available Andrew Jones
2023-02-24 13:58 ` [PATCH] RISC-V: Fixup clear_page export when using Zicboz Ben Dooks
2023-02-24 14:18 ` Andrew Jones
2023-02-24 14:42 ` Ben Dooks
2023-02-24 15:19 ` Andrew Jones
2023-02-24 14:44 ` Sudip Mukherjee
2023-02-24 15:11 ` Andrew Jones
2023-02-24 14:00 ` [PATCH v5 6/8] RISC-V: Use Zicboz in clear_page when available Ben Dooks
2023-02-24 14:25 ` Andrew Jones
2023-02-24 14:36 ` Andrew Jones
2023-02-21 19:09 ` [PATCH v5 7/8] RISC-V: KVM: Provide UAPI for Zicboz block size Andrew Jones
2023-02-21 19:09 ` [PATCH v5 8/8] RISC-V: KVM: Expose Zicboz to the guest Andrew Jones
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