From: Andrew Jones <ajones@ventanamicro.com>
To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
kvm-riscv@lists.infradead.org
Cc: 'Rob Herring ' <robh@kernel.org>,
'Jisheng Zhang ' <jszhang@kernel.org>,
'Anup Patel ' <apatel@ventanamicro.com>,
'Conor Dooley ' <conor.dooley@microchip.com>,
'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org>,
'Heiko Stuebner ' <heiko@sntech.de>,
'Paul Walmsley ' <paul.walmsley@sifive.com>,
'Palmer Dabbelt ' <palmer@dabbelt.com>,
'Albert Ou ' <aou@eecs.berkeley.edu>,
'Ben Dooks ' <ben.dooks@codethink.co.uk>,
'Atish Patra ' <atishp@rivosinc.com>,
Anup Patel <anup@brainfault.org>
Subject: [PATCH v5 8/8] RISC-V: KVM: Expose Zicboz to the guest
Date: Tue, 21 Feb 2023 20:09:16 +0100 [thread overview]
Message-ID: <20230221190916.572454-9-ajones@ventanamicro.com> (raw)
In-Reply-To: <20230221190916.572454-1-ajones@ventanamicro.com>
Guests may use the cbo.zero instruction when the CPU has the Zicboz
extension and the hypervisor sets henvcfg.CBZE.
Add Zicboz support for KVM guests which may be enabled and
disabled from KVM userspace using the ISA extension ONE_REG API.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index c1a1bb0fa91c..e44c1e90eaa7 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -106,6 +106,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_SVINVAL,
KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
KVM_RISCV_ISA_EXT_ZICBOM,
+ KVM_RISCV_ISA_EXT_ZICBOZ,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index e5126cefbc87..198ee86cad38 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -63,6 +63,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(SVPBMT),
KVM_ISA_EXT_ARR(ZIHINTPAUSE),
KVM_ISA_EXT_ARR(ZICBOM),
+ KVM_ISA_EXT_ARR(ZICBOZ),
};
static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -865,6 +866,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
if (riscv_isa_extension_available(isa, ZICBOM))
henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
+ if (riscv_isa_extension_available(isa, ZICBOZ))
+ henvcfg |= ENVCFG_CBZE;
+
csr_write(CSR_HENVCFG, henvcfg);
#ifdef CONFIG_32BIT
csr_write(CSR_HENVCFGH, henvcfg >> 32);
--
2.39.1
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prev parent reply other threads:[~2023-02-21 20:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 19:09 [PATCH v5 0/8] RISC-V: Apply Zicboz to clear_page Andrew Jones
2023-02-21 19:09 ` [PATCH v5 1/8] RISC-V: alternatives: Support patching multiple insns in assembly Andrew Jones
2023-02-21 19:09 ` [PATCH v5 2/8] RISC-V: Factor out body of riscv_init_cbom_blocksize loop Andrew Jones
2023-02-21 19:09 ` [PATCH v5 3/8] dt-bindings: riscv: Document cboz-block-size Andrew Jones
2023-02-21 19:09 ` [PATCH v5 4/8] RISC-V: Add Zicboz detection and block size parsing Andrew Jones
2023-02-21 19:09 ` [PATCH v5 5/8] riscv: cpufeatures: Put the upper 16 bits of patch ID to work Andrew Jones
2023-02-22 17:27 ` Conor Dooley
2023-02-23 12:53 ` Andrew Jones
2023-02-21 19:09 ` [PATCH v5 6/8] RISC-V: Use Zicboz in clear_page when available Andrew Jones
2023-02-24 13:58 ` [PATCH] RISC-V: Fixup clear_page export when using Zicboz Ben Dooks
2023-02-24 14:18 ` Andrew Jones
2023-02-24 14:42 ` Ben Dooks
2023-02-24 15:19 ` Andrew Jones
2023-02-24 14:44 ` Sudip Mukherjee
2023-02-24 15:11 ` Andrew Jones
2023-02-24 14:00 ` [PATCH v5 6/8] RISC-V: Use Zicboz in clear_page when available Ben Dooks
2023-02-24 14:25 ` Andrew Jones
2023-02-24 14:36 ` Andrew Jones
2023-02-21 19:09 ` [PATCH v5 7/8] RISC-V: KVM: Provide UAPI for Zicboz block size Andrew Jones
2023-02-21 19:09 ` Andrew Jones [this message]
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