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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id j9-20020aa79289000000b0058db8f8bce8sm1533758pfa.166.2023.03.10.07.07.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Mar 2023 07:07:59 -0800 (PST) From: Bin Meng To: conor@kernel.org Cc: aurelien@aurel32.net, conor.dooley@microchip.com, linux-riscv@lists.infradead.org, llvm@lists.linux.dev, naresh.kamboju@linaro.org, nathan@kernel.org, ndesaulniers@google.com, palmer@dabbelt.com, palmer@rivosinc.com, stable@vger.kernel.org Subject: Re: [PATCH v2] RISC-V: remove I-extension ISA spec version dance Date: Fri, 10 Mar 2023 23:07:54 +0800 Message-Id: <20230310150754.535425-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230308220842.1231003-1-conor@kernel.org> References: <20230308220842.1231003-1-conor@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230310_070804_285075_3D2C8AFE X-CRM114-Status: GOOD ( 31.90 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org > From: Conor Dooley > > The spec folk, in their infinite wisdom, moved both control and status > registers & the FENCE.I instructions out of the I extension into their > own extensions (Zicsr, Zifencei) in the 20190608 version of the ISA > spec [0]. > The GCC/binutils crew decided [1] to move their default version of the > ISA spec to the 20191213 version of the ISA spec, which came into being > for version 2.38 of binutils and GCC 12. Building with this toolchain > configuration would result in assembler issues: > CC arch/riscv/kernel/vdso/vgettimeofday.o > <>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: > <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > This was fixed in commit 6df2a016c0c8 ("riscv: fix build with binutils > 2.38") by Aurelien Jarno, but has proven fragile. > > Before LLVM 17, LLVM did not support these extensions and, as such, the > cc-option check added by Aurelien worked. Since commit 22e199e6afb1 > ("[RISCV] Accept zicsr and zifencei command line options") however, LLVM > *does* support them and the cc-option check passes. > > This surfaced as a problem while building the 5.10 stable kernel using > the default Tuxmake Debian image [2], as 5.10 did not yet support ld.lld, > and uses the Debian provided binutils 2.35. > Versions of ld prior to 2.38 will refuse to link if they encounter > unknown ISA extensions, and unfortunately Zifencei is not supported by > bintuils 2.35. > > Instead of dancing around with adding these extensions to march, as we > currently do, Palmer suggested locking GCC builds to the same version of > the ISA spec that is used by LLVM. As far as I can tell, that is 2.2, > with, apparently [3], a lack of interest in implementing a flag like > GCC's -misa-spec at present. > > Add {cc,as}-option checks to add -misa-spec to KBUILD_{A,C}FLAGS when > GCC is used & remove the march dance. > > As clang does not accept this argument, I had expected to encounter > issues with the assembler, as neither zicsr nor zifencei are present in > the ISA string and the spec version *should* be defaulting to a version > that requires them to be present. The build passed however and the > resulting kernel worked perfectly fine for me on a PolarFire SoC... > > Link: https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf [0] > Link: https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4 [1] > Link: https://lore.kernel.org/all/CA+G9fYt9T=ELCLaB9byxaLW2Qf4pZcDO=huCA0D8ug2V2+irJQ@mail.gmail.com/ [2] > Link: https://discourse.llvm.org/t/specifying-unpriviledge-spec-version-misa-spec-gcc-flag-equivalent/66935 [3] > CC: stable@vger.kernel.org > Suggested-by: Palmer Dabbelt > Reported-by: Naresh Kamboju > Signed-off-by: Conor Dooley > --- > I think Aurelien's original commit message might actually not be quite > correct? I found, in my limited testing, that it is not the default > behaviour of gas that matters, but rather the toolchain itself? > My binutils versions (both those built using the clang-built-linux > tc-build scripts which do not set an ISA spec version, and one built > using the riscv-gnu-toolchain infra w/ an explicit 20191213 spec version > set) do not encounter these issues. I am unable to reproduce the build failure as reported by commit 6df2a016c0c8 ("riscv: fix build with binutils 2.38") by Aurelien Jarno using kernel.org pre-built GCC 11.3.0 [1] which includes binutils 2.38. [1] https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.3.0/x86_64-gcc-11.3.0-nolibc-x86_64-linux.tar.xz The defconfig of v5.16 kernel (commit 6df2a016c0c8 lands in v5.17) builds fine for me. Anything I am missing? > >From *my* testing, I was only able to reproduce the above build failures > because of *GCC* defaulting to a newer ISA spec version, and saw no > issues with CC=clang builds, where -misa-spec is not (AFAICT) passed to > gas. > I'm far from a toolchain person, so I am very very happy to have the > reason for that explained to me, as I've been scratching my head about > it all evening. > > I'm also not super confident in my "as-option"ing, but it worked for me, > so it's gotta be perfect, right? riiight?? > > Changes from v1: > - entirely new approach to the issue > --- > arch/riscv/Makefile | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 6203c3378922..2df7a5dc071c 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -57,10 +57,8 @@ riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > > -# Newer binutils versions default to ISA spec version 20191213 which moves some > -# instructions from the I extension to the Zicsr and Zifencei extensions. > -toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > -riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > +KBUILD_CFLAGS += $(call cc-option,-misa-spec=2.2) > +KBUILD_AFLAGS += $(call as-option,-Wa$(comma)-misa-spec=2.2) > > # Check if the toolchain supports Zihintpause extension > riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause > -- _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv