From: Conor Dooley <conor.dooley@microchip.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>, <kvm@vger.kernel.org>,
<kvm-riscv@lists.infradead.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v3 2/8] RISC-V: Detect AIA CSRs from ISA string
Date: Mon, 3 Apr 2023 10:39:46 +0100 [thread overview]
Message-ID: <20230403-80af54e80a34fc70fad04e0c@wendy> (raw)
In-Reply-To: <20230403093310.2271142-3-apatel@ventanamicro.com>
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On Mon, Apr 03, 2023 at 03:03:04PM +0530, Anup Patel wrote:
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 59d58ee0f68d..1b13a5823b90 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -221,8 +221,10 @@ void __init riscv_fill_hwcap(void)
> }
> } else {
> /* sorted alphabetically */
^^^^^^^^^^^^^^^^^^^^^
> + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
> SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
> SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
> + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
This entry has been added in an incorrect order chief :/
> SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
> SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
> SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
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next prev parent reply other threads:[~2023-04-03 9:40 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-03 9:33 [PATCH v3 0/8] RISC-V KVM virtualize AIA CSRs Anup Patel
2023-04-03 9:33 ` [PATCH v3 1/8] RISC-V: Add AIA related CSR defines Anup Patel
2023-04-03 9:33 ` [PATCH v3 2/8] RISC-V: Detect AIA CSRs from ISA string Anup Patel
2023-04-03 9:39 ` Conor Dooley [this message]
2023-04-03 12:05 ` Anup Patel
2023-04-03 9:33 ` [PATCH v3 3/8] RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID mask defines Anup Patel
2023-04-03 9:33 ` [PATCH v3 4/8] RISC-V: KVM: Initial skeletal support for AIA Anup Patel
2023-04-03 12:00 ` Andrew Jones
2023-04-03 23:49 ` Atish Patra
2023-04-04 3:22 ` Anup Patel
2023-04-03 9:33 ` [PATCH v3 5/8] RISC-V: KVM: Implement subtype for CSR ONE_REG interface Anup Patel
2023-04-03 12:18 ` Andrew Jones
2023-04-04 0:54 ` Atish Patra
2023-04-03 9:33 ` [PATCH v3 6/8] RISC-V: KVM: Add ONE_REG interface for AIA CSRs Anup Patel
2023-04-03 11:31 ` Andrew Jones
2023-04-03 12:04 ` Anup Patel
2023-04-03 12:23 ` Andrew Jones
2023-04-04 11:52 ` Andrew Jones
2023-04-04 11:58 ` Conor Dooley
2023-04-05 9:28 ` Conor Dooley
2023-04-04 12:03 ` Andrew Jones
2023-04-03 12:27 ` Andrew Jones
2023-04-04 0:55 ` Atish Patra
2023-04-03 9:33 ` [PATCH v3 7/8] RISC-V: KVM: Virtualize per-HART " Anup Patel
2023-04-03 16:37 ` Andrew Jones
2023-04-04 13:31 ` Anup Patel
2023-04-04 13:54 ` Anup Patel
2023-04-03 9:33 ` [PATCH v3 8/8] RISC-V: KVM: Implement guest external interrupt line management Anup Patel
2023-04-04 12:45 ` Andrew Jones
2023-04-04 13:52 ` Anup Patel
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