From: Drew Fustini <dfustini@baylibre.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Atish Patra" <atishp@rivosinc.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"James Morse" <james.morse@arm.com>,
"Kornel Dulęba" <mindal@semihalf.com>,
"Adrien Ricciardi" <aricciardi@baylibre.com>
Cc: Drew Fustini <dfustini@baylibre.com>
Subject: [RFC PATCH 1/2] RISC-V: Detect the Ssqosid extension
Date: Sun, 9 Apr 2023 21:36:45 -0700 [thread overview]
Message-ID: <20230410043646.3138446-2-dfustini@baylibre.com> (raw)
In-Reply-To: <20230410043646.3138446-1-dfustini@baylibre.com>
From: Kornel Dulęba <mindal@semihalf.com>
Detect the Ssqosid extension (Supervisor-mode Quality of Service ID) as
defined in the CBQRI (Capacity and Bandwidth QoS Register Interface)
specification.
Link: https://github.com/riscv-non-isa/riscv-cmqri/blob/main/riscv-cbqri.pdf
Signed-off-by: Kornel Dulęba <mindal@semihalf.com>
[dfustini: rebase from v6.0 to v6.3]
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
---
Note: the Ssqosid extension and CBQRI spec are still in a draft state.
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
3 files changed, 4 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 9af793970855..6dd717030723 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -44,6 +44,8 @@
#define RISCV_ISA_EXT_ZIHINTPAUSE 32
#define RISCV_ISA_EXT_SVNAPOT 33
#define RISCV_ISA_EXT_ZICBOZ 34
+#define RISCV_ISA_EXT_SSQOSID 35
+
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 9203e18320f9..04bd0a21910e 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -190,6 +190,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
+ __RISCV_ISA_EXT_DATA(ssqosid, RISCV_ISA_EXT_SSQOSID),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 00d7cd2c9043..94bf5556347d 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -226,6 +226,7 @@ void __init riscv_fill_hwcap(void)
} else {
/* sorted alphabetically */
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
+ SET_ISA_EXT_MAP("ssqosid", RISCV_ISA_EXT_SSQOSID);
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
--
2.34.1
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next prev parent reply other threads:[~2023-04-10 4:34 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-10 4:36 [RFC PATCH 0/2] RISC-V: Detect Ssqosid extension and handle sqoscfg CSR Drew Fustini
2023-04-10 4:36 ` Drew Fustini [this message]
2023-04-10 4:36 ` [RFC PATCH 2/2] RISC-V: Add support for " Drew Fustini
2023-04-17 19:10 ` Conor Dooley
2023-04-17 20:04 ` Drew Fustini
2023-04-21 9:34 ` Conor Dooley
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