[PATCH 0/2] RISC-V: hwprobe: Couple fixes found on late review

[PATCH 0/2] RISC-V: hwprobe: Couple fixes found on late review

[Andrew Jones]

I didn't get a chance to take a close look at "[PATCH v6 0/6] RISC-V
Hardware Probing User Interface" until now. I spotted a couple issues
while looking and this series collects the fixes.

Andrew Jones (2):
  RISC-V: hwprobe: There can only be one first
  RISC-V: hwprobe: Explicity check for -1 in vdso init

 arch/riscv/kernel/sys_riscv.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

-- 
2.39.2


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[PATCH 1/2] RISC-V: hwprobe: There can only be one first

[Andrew Jones]

Only capture the first cpu_id in order for the comparison
below to be of any use.

Fixes: ea3de9ce8aa2 ("RISC-V: Add a syscall for HW probing")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/kernel/sys_riscv.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 849b4170629d..c569dac7452e 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -103,8 +103,10 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair,
 			break;
 		}
 
-		if (first)
+		if (first) {
 			id = cpu_id;
+			first = false;
+		}
 
 		/*
 		 * If there's a mismatch for the given set, return -1 in the
-- 
2.39.2


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[PATCH 2/2] RISC-V: hwprobe: Explicity check for -1 in vdso init

[Andrew Jones]

id_bitsmash is unsigned. We need to explicitly check for -1, rather
than use > 0.

Fixes: aa5af0aa90ba ("RISC-V: Add hwprobe vDSO function and data")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/kernel/sys_riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index c569dac7452e..5db29683ebee 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -282,7 +282,7 @@ static int __init init_hwprobe_vdso_data(void)
 	 * populated) or any value returns -1 (varies across CPUs), then the
 	 * vDSO should defer to the kernel for exotic cpu masks.
 	 */
-	avd->homogeneous_cpus = (id_bitsmash > 0);
+	avd->homogeneous_cpus = id_bitsmash != 0 && id_bitsmash != -1;
 	return 0;
 }
 
-- 
2.39.2


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Re: [PATCH 0/2] RISC-V: hwprobe: Couple fixes found on late review

[Conor Dooley]

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On Wed, Apr 26, 2023 at 04:13:31PM +0200, Andrew Jones wrote:
> I didn't get a chance to take a close look at "[PATCH v6 0/6] RISC-V
> Hardware Probing User Interface" until now. I spotted a couple issues
> while looking and this series collects the fixes.

Both seem fair..
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

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Re: [PATCH 0/2] RISC-V: hwprobe: Couple fixes found on late review

[Evan Green]

On Wed, Apr 26, 2023 at 7:13 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> I didn't get a chance to take a close look at "[PATCH v6 0/6] RISC-V
> Hardware Probing User Interface" until now. I spotted a couple issues
> while looking and this series collects the fixes.
>
> Andrew Jones (2):
>   RISC-V: hwprobe: There can only be one first
>   RISC-V: hwprobe: Explicity check for -1 in vdso init
>
>  arch/riscv/kernel/sys_riscv.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> --
> 2.39.2

Sigh, wish I had spotted these. Thanks!

Reviewed-by: Evan Green <evan@rivosinc.com>

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Re: [PATCH 0/2] RISC-V: hwprobe: Couple fixes found on late review

[Palmer Dabbelt]

On Wed, 26 Apr 2023 16:13:31 +0200, Andrew Jones wrote:
> I didn't get a chance to take a close look at "[PATCH v6 0/6] RISC-V
> Hardware Probing User Interface" until now. I spotted a couple issues
> while looking and this series collects the fixes.
> 
> Andrew Jones (2):
>   RISC-V: hwprobe: There can only be one first
>   RISC-V: hwprobe: Explicity check for -1 in vdso init
> 
> [...]

Applied, thanks!

[1/2] RISC-V: hwprobe: There can only be one first
      https://git.kernel.org/palmer/c/08dc10759468
[2/2] RISC-V: hwprobe: Explicity check for -1 in vdso init
      https://git.kernel.org/palmer/c/b09313dd2e72

Best regards,
-- 
Palmer Dabbelt <palmer@rivosinc.com>


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