Re: [PATCH v2 1/2] riscv: allow case-insensitive ISA string parsing

Conor Dooley
2023-04-28T19:28:13Z

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Hey Yangyu,

On Fri, Apr 28, 2023 at 10:16:00PM +0800, Yangyu Chen wrote:
> According to RISC-V Hart Capabilities Table (RHCT) description in UEFI
> Forum ECR, the format of the ISA string is defined in the RISC-V
> unprivileged specification which is case-insensitive. However, the
> current ISA string parser in the kernel does not support ISA strings
> with uppercase letters.
>
> This patch modifies the ISA string parser in the kernel to support
> case-insensitive ISA string parsing.

@Palmer, @Sunil
Just to note, we probably should get this applied *before* we enable ACPI,
right?

>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
> arch/riscv/kernel/cpu.c | 3 ++-
> arch/riscv/kernel/cpufeature.c | 25 ++++++++++++-------------
> 2 files changed, 14 insertions(+), 14 deletions(-)

> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 59d58ee0f68d..d1991c12e546 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -119,13 +119,10 @@ void __init riscv_fill_hwcap(void)
> }
>
> temp = isa;
> -#if IS_ENABLED(CONFIG_32BIT)
> - if (!strncmp(isa, "rv32", 4))
> + if (IS_ENABLED(CONFIG_32BIT) && !strncasecmp(isa, "rv32", 4))
> isa += 4;
> -#elif IS_ENABLED(CONFIG_64BIT)
> - if (!strncmp(isa, "rv64", 4))
> + else if (IS_ENABLED(CONFIG_64BIT) && !strncasecmp(isa, "rv64", 4))
> isa += 4;
> -#endif
> /* The riscv,isa DT property must start with rv64 or rv32 */
> if (temp == isa)
> continue;
> @@ -136,6 +133,7 @@ void __init riscv_fill_hwcap(void)
> bool ext_long = false, ext_err = false;
>
> switch (*ext) {
> + case 'S':

Capital S should never be emitted by QEMU, so there's no need to have
this use the workaround, right? IOW, move it between s & X.

Otherwise, this looks good to me:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.